Teaching Hardware Design of Fixed-Point Digital Signal Processing Systems

Signal processing theory and practice are enabling and driving forces behind multimedia devices, communications systems, and even such diverse fields as automotive and medical systems. Over 90 % of the signal processing systems on the market used fixed-point arithmetic because of the cost, power, and area savings that fixed-point systems provide. However, most colleges and universities do not teach or teach only a very little fixed-point signal processing. This issue is being addressed slowly around the country but now a new challenge or opportunity presents itself. As reconfigurable logic technology matures, field-programmable gate arrays (FPGAs) are increasingly used for signal processing systems. They have the advantage of tremendous throughput, great flexibility, and system integration. The challenge is that signal processing in FPGAs is a much less constrained problem than signal processing in special purpose microprocessors. The opportunity arises in that it is now possible to explore more options and, more especially, to take a more systems-level approach to signal processing systems. In short, designing a signal processing system using FPGAs provides opportunities to look at many system design issues and trade-offs in a classroom setting. We have developed a course to teach signal processing in FPGAs at Georgia Institute of Technology and in this paper we consider the challenges and methods of teaching fixedpoint system design in this course. We discuss the topics chosen and how they differ from traditional microprocessor-based courses. We also discuss how systems engineering concepts are woven into the course.

Hardware Components in Cybersecurity Education

Hardware components have been designated as required academic content for colleges to be recognized as a center of academic excellence in cyber operations by the National Security Agency (NSA). To meet the hardware requirement, computer science and information technology programs must cover hardware concepts and design skills, topics which are less emphasized in existing programs. This paper describes a new pedagogical model for hardware based on network intrusion detection taught at college and graduate levels in a National Center of Academic Excellence in Information Assurance Education Program (CAE/IAE). The curriculum focuses on the fundamental concepts of network intrusion detection mechanisms, network traffic analysis, rule-based detection logic, system configuration, and basic hardware design and experiments. This new course enriches students with the latest developments

The Megaprocessor as an Educational Tool Making the Abstract Concrete

Computer architecture courses can be difficult for students to engage with and learn from. This is because, unlike most core courses for a computer science student, learning architecture is an abstract process. To address this, universities have implemented methods for teaching course material other than purely descriptive methods. This typically means using simulations to model some aspect of a CPU or FPGA (fieldprogrammable gate array) boards for hands-on experimentation in CPU design. However, there are issues with these tools. Simulations can only cover a few topics well, are prone to being abandoned, and introduce additional abstraction layers. FPGAs, while great for advanced topics and long class projects, are often best suited for senior and graduate level students. Both methods are useful, but neither offers a tangible learning experience, which is what the Megaprocessor can provide. The Megaprocessor is a room sized, general-purpose computer made from discrete components, whose architecture is comprised of primitive logic gates with LEDs on every input and output. The entire circuitry of the Megaprocessor is transparent to the users, with its entire state visible and unabstracted. Because of these properties, it is a great learning mechanism for computer architecture education. The Megaprocessor is a tool for hands on and project-based learning that can be used to span the learning gap between simulations and FPGAs

Undergraduate curriculum to teach and provide research skills on hardware design for SDR applications in FPGA technology

Software Defined Radio (SDR) technologies play today an important role in modern wireless networks due to their flexibility to implement re-configurable hardware designs. In light of the importance to operate and develop such technologies, academic programs in the communications engineering field demand an introduction to Digital Signal Processing (DSP) and SDR communication schemes accordingly. Typically, the teaching of this subject is afforded through projects and hands-on activities in classrooms. However, provided their relevance in the current state-of-the-art, this topic also provides a framework to teach soft skills concerning research abilities in students. This paper introduces an academic program to the development of SDR functionality as well as research skills based on exposure to state-of-the-art research. Through projects, hands-on activities are conducted to teach digital signal processing designs using Field Programmable Gate Array (FPGA) technology. The course aims to develop technical skills to implement communication system blocks. Besides, workshops and seminars are prepared to support the development of research and communication skills. The proposed course is flexible to incorporate on a given academic program as an elective subject to further support topics related to communication theory and discrete-time signals. Learning outcomes are designed to develop enhanced technical skills in SDR design and simultaneously a critical discussion of the devised solutions in light of the state-of-the-art. Also, skills related to identifying, formulating, and discussing engineering problems are further reinforced. Results from supported projects developed in the classroom exhibit completed assignments superior to 90% of participant students. Learning objectives concerning the technical skills were successfully covered (90%) in comparison to research and communicating skills (80%). Additionally, research skills and the ability to disseminate knowledge gradually improved in seminars. Finally, results of the current course exhibit improvements of 25% regarding the acquired skills in digital signal processing in comparison to previous courses.This work was supported in part by the Spanish National Project Hybrid Terrestrial/Satellite Air Interface for 5G and Beyond-Areas of Diffcult Access (TERESA-ADA) through the [Ministerio de Economía, Industria y Competitividad (MINECO)/Agencia Estatal de Investigación (AEI)/Fondo Europeo de Desarrollo Regional (FEDER), Unión Europea (UE)] under Grant TEC2017-90093-C3-2-R.Publicad

Remote Laboratory for E-Learning of Systems on Chip and Their Applications to Nuclear and Scientific Instrumentation

Configuring and setting up a remote access laboratory for an advanced online school on fully programmable System-on-Chip (SoC) proved to be an outstanding challenge. The school, jointly organized by the International Centre for Theoretical Physics (ICTP) and the International Atomic Energy Agency (IAEA), focused on SoC and its applications to nuclear and scientific instrumentation and was mainly addressed to physicists, computer scientists and engineers from developing countries. The use of e-learning tools, which some of them adopted and others developed, allowed the school participants to directly access both integrated development environment software and programmable SoC platforms. This facilitated the follow-up of all proposed exercises and the final project. During the four weeks of the training activity, we faced and overcame different technology and communication challenges, whose solutions we describe in detail together with dedicated tools and design methodology. We finally present a summary of the gained experience and an assessment of the results we achieved, addressed to those who foresee to organize similar initiatives using e-learning for advanced training with remote access to SoC platforms

NetFPGA: status, uses, developments, challenges, and evaluation

The constant growth of the Internet, driven by the demand for timely access to data center networks; has meant that the technological platforms necessary to achieve this purpose are outside the current budgets. In this order to make and validate relevant, timely and relevant contributions; it is necessary that a wider community, access to evaluation, experimentation and demonstration environments with specifications that can be compared with existing networking solutions. This article introduces the NetFPGA, which is a platform to develop network hardware for reconfigurable and rapid prototyping. It’s introduces the application areas in high-performance networks, advantages for traffic analysis, packet flow, hardware acceleration, power consumption and parallel processing in real time. Likewise, it presents the advantages of the platform for research, education, innovation, and future trends of this platform. Finally, we present a performance evaluation of the tool called OSNT (Open-Source Network Tester) and shows that OSNT has 95% accuracy of timestamp with resolution of 10ns for the generation of TCP traffic, and 90% efficiency capturing packets at 10Gbps of full line-rate