Optimization of multi-gigabit transceivers for high speed data communication links in HEP Experiments

The scheme of the data acquisition (DAQ) architecture in High Energy Physics (HEP) experiments consist of data transport from the front-end electronics (FEE) of the online detectors to the readout units (RU), which perform online processing of the data, and then to the data storage for offline analysis. With major upgrades of the Large Hadron Collider (LHC) experiments at CERN, the data transmission rates in the DAQ systems are expected to reach a few TB/sec within the next few years. These high rates are normally associated with the increase in the high-frequency losses, which lead to distortion in the detected signal and degradation of signal integrity. To address this, we have developed an optimization technique of the multi-gigabit transceiver (MGT) and implemented it on the state-of-the-art 20nm Arria-10 FPGA manufactured by Intel Inc. The setup has been validated for three available high-speed data transmission protocols, namely, GBT, TTC-PON and 10 Gbps Ethernet. The improvement in the signal integrity is gauged by two metrics, the Bit Error Rate (BER) and the Eye Diagram. It is observed that the technique improves the signal integrity and reduces BER. The test results and the improvements in the metrics of signal integrity for different link speeds are presented and discussed

Integrated Transversal Equalizers in High-Speed Fiber-Optic Systems

Intersymbol interference (ISI) caused by intermodal dispersion in multimode fibers is the major limiting factor in the achievable data rate or transmission distance in high-speed multimode fiber-optic links for local area networks applications. Compared with optical-domain and other electrical-domain dispersion compensation methods, equalization with transversal filters based on distributed circuit techniques presents a cost-effective and low-power solution. The design of integrated distributed transversal equalizers is described in detail with focus on delay lines and gain stages. This seven-tap distributed transversal equalizer prototype has been implemented in a commercial 0.18-µm SiGe BiCMOS process for 10-Gb/s multimode fiber-optic links. A seven-tap distributed transversal equalizer reduces the ISI of a 10-Gb/s signal after 800 m of 50-µm multimode fiber from 5 to 1.38 dB, and improves the bit-error rate from about 10^-5 to less than 10^-12

The AURORA Gigabit Testbed

AURORA is one of five U.S. networking testbeds charged with exploring applications of, and technologies necessary for, networks operating at gigabit per second or higher bandwidths. The emphasis of the AURORA testbed, distinct from the other four testbeds, BLANCA, CASA, NECTAR, and VISTANET, is research into the supporting technologies for gigabit networking. Like the other testbeds, AURORA itself is an experiment in collaboration, where government initiative (in the form of the Corporation for National Research Initiatives, which is funded by DARPA and the National Science Foundation) has spurred interaction among pre-existing centers of excellence in industry, academia, and government. AURORA has been charged with research into networking technologies that will underpin future high-speed networks. This paper provides an overview of the goals and methodologies employed in AURORA, and points to some preliminary results from our first year of research, ranging from analytic results to experimental prototype hardware. This paper enunciates our targets, which include new software architectures, network abstractions, and hardware technologies, as well as applications for our work

Sistemas de calibração automático para transceivers NG-PON2

The current society is increasingly dependent on communication services, requiring better and faster connections, predicting in a near future connections in the order of hundreds of Gbit/s. During the data transmissions, the increase of speed reflects an increase of the error ratio due to factors such as noise, reductions of signal or jitter, which for low speed these were not emphasized so much. This project involves the development of a BER test system for both continuous and Burst mode of the transmission, demonstrating the viability of communication over the next-generation technology, NG-PON2, which uses high transmission rates (10 Gbit/s). For this purpose, an FPGA architecture was implemented that allows for long distances in the optical network, high transmission rates. This choice reflects a more economical alternative in relation to commercial equipment and has several advantages, such as the flexibility to reprogram and prepare the architecture according to the needs of the user. To achieve the proposed requirements, the project was divided into three parts. In the first part an architecture was developed that allows to obtain the error rate during a continuous mode transmission. In order to obtain the real-time viability of the communication referred and to have control over the system, an interface was developed between the computer and the FPGA to change certain characteristics of the communication channel. This is the second part of the project. The last part of the project has an architecture similar to the previous one, that is, instead of the transmission to be done in continuous mode, it is performed in mode Burst, being this the requirement with more interest to the technology NG-PON2. Finally, proof of concept was performed through an optical network provided by the company PICadvanced that allowed the validation of the different parts of the project. These validations will allow the development of new modules that will later contribute to the main project that is under development in the company PICadvanced, which aims at the construction of an automatic calibration board for the XFP transceivers.A sociedade atual depende cada vez mais dos serviços de comunicação, exigindo melhores ligações e mais rápidas, prevendo-se num futuro próximo a necessidade de ligações na ordem das centenas de Gbit/s. O aumento dos ritmos de transmissão refletem um aumento no que se refere à taxa de erro (BER), uma vez que o impacto associado a fatores como ruı́do ou interferência entre sı́mbolos, é maior do que para baixos ritmos. Este trabalho foca-se no desenvolvimento de um sistema de teste BER, tanto para uma transmissão contı́nua como para transmissão em rajadas, que demonstre a viabilidade da comunicação sobre a tecnologia da próxima geração, Next Generation Passive Optical Network 2 (NG-PON2), que utiliza débitos de transmissão elevados (10 Gbit/s). Para este efeito foi implementado uma arquitetura em Field-programmable gate array (FPGA) que possibilita para longas distâncias na rede ótica, elevados ritmos de transmissão. Esta escolha reflete uma alterativa mais económica em relação aos equipamentos comerciais e apresenta vantagens tais como a flexibilidade de reprogramar e preparar a arquitetura de acordo com as necessidades do utilizador. Para cumprir os requisitos propostos o projeto dividiu-se em três partes. Numa primeira parte do projeto desenvolveu-se uma arquitetura que permite adquirir a taxa de erros durante uma transmissão contı́nua. Com o intuito de analisar a viabilidade em tempo real da comunicação em questão, bem com o utilizador ter controlo sobre o sistema, alterando certas caracterı́sticas do canal de comunicação, desenvolveu-se numa segunda parte do projeto uma interface entre o computador e a FPGA. Numa última parte do projeto desenvolveu-se uma arquitetura semelhante à anterior, na qual se permite igualmente adquirir a taxa de erros com transmissão em rajadas (Burst), sendo este um dos requisitos de maior interesse na tecnologia NG-PON2. Por fim, a prova de conceito foi realizada através de uma rede ótica disponibilizada pela empresa PICadvanced, que permitiu a validação das diversas partes do projeto. Estas validações vão permitir a conceção de novos módulos que posteriormente vão contribuir para o projeto fonte que está em desenvolvimento na empresa PICadvanced, que visa a implementação de uma placa de calibração automatizada para os transceptores 10 Gigabit Small Form Factor Pluggables (XFP).Mestrado em Engenharia Eletrónica e Telecomunicaçõe

High-Speed Low-Voltage Line Driver for SerDes Applications

The driving factor behind this research was to design & develop a line driver capable of meeting the demanding specifications of the next generation of SerDes devices. In this thesis various line driver topologies were analysed to identify a topology suited for a high-speed low-voltage operating environment. This thesis starts of by introducing a relatively new high-speed communication Device called SerDes. SerDes is used in wired chip-to-chip communications and operates by converting a parallel data stream in a serial data stream that can be then transmitted at a higher bit rate, existing SerDes devices operate up to 12.5Gbps. A matching SerDes device at the destination will then convert the serial data stream back into a parallel data stream to be read by the destination ASIC. SerDes typically uses a line driver with a differential output. Using a differential line driver increases the resilience to outside sources of noise and reduces the amount of EM radiation produced by transmission. The focus of this research is to design and develop a line driver that can operate at 40Gbps and can function with a power supply of less than IV. This demanding specification was decided to be an accurate representation of future requirements that a line driver in a SerDes device will have to conform to. A suitable line driver with a differential output was identified to meet the demanding specifications and was modified so that it can perfonn an equalisation technique called pre-distortion. Two variations of the new topology were outlined and a behavioural model was created for both using Matlab Simulink. The behavioural model for both variants proved the concept, however only one variant maintained its perfomance once the designs were implemented at transistor level in Cadence, using a 65nm CMOS technology provided by Texas Instruments. The final line driver design was then converted into a layout design, again using Cadence, and RC parasitics were extracted to perfom a post-layout simulation. The post layout simulation shows that the novel line driver can operate at 40Gbps with a power supply of 1 V - O.8V and has a power consumption of 4.54m W /Gbps. The Deterministic Jitter added by the line driver is 12.9ps

Sistemas de teste automáticos para transceivers NG-PON2

Optical communications have had a fundamental role in conecting people worldwide. More than ever, there has been an incessant necessity to turn technology more ubiquitous With recent advancements in optical technology, it has become possible to keep up with the demand for higher transmission rates in upstream or downstream, higher bandwidth e still guaranteeing Quality of Service (QoS) among inumerous users This emerging necessity has taken telecommunication companies to inovate in the area of development regarding optical equipment and also dealing with the referred necessities. For this to happen, good quality control, calibration e testing of produced parts is of paramount importance. The work cut out for this dissertation is focused on the improvement and addition of funtionalities to a test-board designed to perform measurements of BER levels, calibration and maintenance of parts according to the newest optical standard(New Gigabit Passive Optical Network 2 (NGPON2)) that operates in maximum rates of 10Gb/s per channel. In the rst part of this work, emphasis is given to the development of a slave Inter Integrated Circuit (I2C) module that ensures connection between the test board and the user, supplying BER values measured through a block dedicated to measure BER levels. Later the same module will allow to access all micro-controlers of the test-board, ensuring calibration functions. On a second part, a characterization of different transceivers of different Field Programmable Gate Array (FPGA)s is performed, consisting of an eye diagram analysis of the transceivers and if possible, to test 10Gb/s continuous mode through BER curves assessing their response. Finally, a comparison is made between all transceivers, the obtained response along with all the respective results, will contribute to the source project of the automatic test board developed at PICadvanced with the intent on evaluating 10 Gigabit Small Form Factor Pluggables (XFP) production.As comunicações têm vindo a ter um papel fundamental em interligar todas as pessoas do mundo. Mais do que nunca, tem havido uma incessante necessidade de tornar a tecnologia mais ubíqua. Com o recente avanço e desenvolvimento da tecnologia Optica, tem sido possível acompanhar a demanda por altas taxas de transmissão em upstream ou downstream, maior largura de banda e ainda garantir Quality of Service (QoS) entre ínumeros utilizadores, etc. . . Esta necessidade emergente tem levado empresas de telecomunicações a inovar na área de desenvolvimento de equipamento óptico e por consequente, comaltar as necessidades referidas. Para isto acontecer tem de haver um bom controlo, calibração e teste de peças produzidas. O trabalho desta dissertação dedica-se ao melhoramento e acrescento de funcionalidades a uma placa de testes desenhada para desempenhar medições de níveis de Bit Error Ratio (BER), calibração e manutenção de peças para o novo standard óptico (New Gigabit Passive Optical Network 2 (NGPON2)) que recorre ao uso de taxas máximas de transmissão de 10Gb/s por canal Na primeira parte do trabalho é dado foco ao desenvolvimento de um módulo escravo Inter Integrated Circuit (I2C) que visa estabelecer o contacto entre a placa de calibração e o utilizador fornecendo os valores de BER medidos através de um bloco dedicado a medir o nível de BER. Mais tarde este módulo servirá para poder aceder aos micro-circuitos da placa de testes podendo realizar funções de calibração. Numa segunda parte, é realizada uma caracterização de diferentes transceivers de diferentes Field Programmable Gate Array (FPGA)s, a caracterização consiste numa análise do diagram de olho de transceivers e ainda sendo possível, testar o modo contínuo nas mesmas, através curvas de BER para avaliar a sua resposta. Por fim, é feita uma comparação entre os mesmos transceivers, além de que todos os resultados obtidos irão contribuir para a o projecto fonte da placa de testes automatizada desenvolvida pela PICadvanced com o intuito de avaliar a produção de 10 Gigabit Small Form Factor Pluggables (XFP).Mestrado em Engenharia Eletrónica e Telecomunicaçõe

Optimization of multi-gigabit transceivers for high speed data communication links in HEP Experiments

The scheme of the data acquisition (DAQ) architecture in High Energy Physics (HEP) experiments consist of data transport from the front-end electronics (FEE) of the online detectors to the readout units (RU), which perform online processing of the data, and then to the data storage for offline analysis. With major upgrades of the Large Hadron Collider (LHC) experiments at CERN, the data transmission rates in the DAQ systems are expected to reach a few TB/sec within the next few years. These high rates are normally associated with the increase in the high-frequency losses, which lead to distortion in the detected signal and degradation of signal integrity. To address this, we have developed an optimization technique of the multi-gigabit transceiver (MGT) and implemented it on the state-of-the-art 20nm Arria-10 FPGA manufactured by Intel Inc. The setup has been validated for three available high-speed data transmission protocols, namely, GBT, TTC-PON and 10 Gbps Ethernet. The improvement in the signal integrity is gauged by two metrics, the Bit Error Rate (BER) and the Eye Diagram. It is observed that the technique improves the signal integrity and reduces BER. The test results and the improvements in the metrics of signal integrity for different link speeds are presented and discussed

Design and implementation of a 10 Gigabit Ethernet XAUI test systems

10 Gigabit Ethernet has been standardized (IEEE 802.3ae), and products based on this standard are being deployed to interconnect MANs, WANs, Storage Area Networks, and very high speed LANs. The XAUI portion of the standard is primarily concerned with short range (up to 50 cm) chip-to-chip communication across printed circuit board traces. The UNH-IOL 10 Gigabit Ethernet Consortium, an industry-supported organization, performs PHY layer testing on products using a test system that has been partially implemented on a Xilinx ML321 evaluation board using the Virtex II-Pro FPGA. A new implementation of the 10 Gigabit Ethernet XAUI test system on the existing ML321 evaluation board is presented in this thesis. The new design removes a number of limitations present in the original Xilinx test system, and it adds new features to the existing transmit and receive sub-systems that enable test engineers to expand the range of test cases and analyze them while simultaneously increasing the speed of testing. The new test system also eliminates the need for expensive test instruments

A High Speed Networked Signal Processing Platform for Multi-element Radio Telescopes

A new architecture is presented for a Networked Signal Processing System (NSPS) suitable for handling the real-time signal processing of multi-element radio telescopes. In this system, a multi-element radio telescope is viewed as an application of a multi-sensor, data fusion problem which can be decomposed into a general set of computing and network components for which a practical and scalable architecture is enabled by current technology. The need for such a system arose in the context of an ongoing program for reconfiguring the Ooty Radio Telescope (ORT) as a programmable 264-element array, which will enable several new observing capabilities for large scale surveys on this mature telescope. For this application, it is necessary to manage, route and combine large volumes of data whose real-time collation requires large I/O bandwidths to be sustained. Since these are general requirements of many multi-sensor fusion applications, we first describe the basic architecture of the NSPS in terms of a Fusion Tree before elaborating on its application for the ORT. The paper addresses issues relating to high speed distributed data acquisition, Field Programmable Gate Array (FPGA) based peer-to-peer networks supporting significant on-the fly processing while routing, and providing a last mile interface to a typical commodity network like Gigabit Ethernet. The system is fundamentally a pair of two co-operative networks, among which one is part of a commodity high performance computer cluster and the other is based on Commercial-Off The-Shelf (COTS) technology with support from software/firmware components in the public domain.Comment: 19 pages, 4 eps figures, To be published in Experimental Astronomy (Springer