Monitoring and Control of Temperature in Networks-on-Chip

Increasing integration densities and the emergence of nanotechnology cause issues related to reliability and power consumption to become dominant factors for the design of modern multi-core systems. Since the arising problems are enforced by high circuit temperatures, monitoring and control of on-chip temperature profiles need to be considered during design phase as well as during system operation. Hence, in this paper different approaches for the realization and integration of a monitoring system for temperature in multi-core systems based on Networks-on-Chip (NoCs) in combination with Dynamic Frequency Scaling (DFS) are investigated. Results show that both combinations using event-driven and time-driven forwarding more than double overall execution time and considerably reduce throughput of application data. Regarding performance of notification and reaction to temperature development event-driven forwarding clearly outperforms time-driven forwarding

Monitoring and Control of Temperature in Networks-on-Chip

Abstract Increasing integration densities and the emergence of nanotechnology cause issues related to reliability and power consumption to become dominant factors for the design of modern multi-core systems. Since the arising problems are enforced by high circuit temperatures, monitoring and control of on-chip temperature profiles need to be considered during design phase as well as during system operation. Hence, in this paper different approaches for the realization and integration of a monitoring system for temperature in multi-core systems based on Networks-on-Chip (NoCs) in combination with Dynamic Frequency Scaling (DFS) are investigated. Results show that both combinations using event-driven and time-driven forwarding more than double overall execution time and considerably reduce throughput of application data. Regarding performance of notification and reaction to temperature development event-driven forwarding clearly outperforms time-driven forwarding

Design of complex integrated systems based on networks-on-chip: Trading off performance, power and reliability

The steady advancement of microelectronics is associated with an escalating number of challenges for design engineers due to both the tiny dimensions and the enormous complexity of integrated systems. Against this background, this work deals with Network-On-Chip (NOC) as the emerging design paradigm to cope with diverse issues of nanotechnology. The detailed investigations within the chapters focus on the communication-centric aspects of multi-core-systems, whereas performance, power consumption as well as reliability are considered likewise as the essential design criteria

Entwicklung einer effizienten Entwurfsraumanalyse zur Optimierung der Leistungsaufnahme von Networks-on-Chip

In der Arbeit werden Networks-on-Chip untersucht. Ein Teil beschäftigt sich mit dem Aufbau und den Eigenschaften von Links bzw. allgemein parallelen on-Chip-Leitungen. Speziell wird auf Crosstalk und eine digitale Methode, diesen Effekt zu messen, eingegangen. Im zweiten Teil der Arbeit wird ein NoC-Router untersucht und dessen Implementierung beschrieben. Aus diesen Erkenntnissen wird eine Methode entwickelt, den Entwurfsraum für ein NoC-basiertes System zu analysieren und so die optimale Kommunikationsarchitektur für eine bestimmte Anwendung zu bestimmen