A Multi-Floor Arrayed Waveguide Grating Based Architecture with Grid Topology for Datacenter Networks

This paper proposes a grid topology based passive optical interconnect (POI) architecture that is composed of multiple floors of arrayed waveguide grating routers (AWGRs) to offer high connectivity and scalability for datacenter networks. In the proposed POI signal only needs to pass one AWGR, and thus can avoid the crosstalk accumulation and cascaded filtering effects, which exist in many existing POI architectures based on cascaded AWGRs. Meanwhile, due to high connectivity, the proposed grid topology based POI also has the potential advantage of high reliability. Simulation results validate the network performance. With a proper node degree, the proposed grid topology can achieve acceptable blocking probability. Besides, steady performance is kept when the number of floors increases, indicating good scalability of the proposed POI

All-Optical Programmable Disaggregated Data Centre Network realized by FPGA-based Switch and Interface Card

This paper reports an FPGA-based switch and interface card (SIC) and its application scenario in an all-optical, programmable disaggregated data center network (DCN). Our novel SIC is designed and implemented to replace traditional optical network interface cards, plugged into the server directly, supporting optical packet switching (OPS)/optical circuit switching (OCS) or time division multiplexing (TDM)/wavelength division multiplexing (WDM) traffic on demand. Placing the SIC in each server/blade, we eliminate electronics from the top of rack (ToR) switch by pushing all the functionality on each blade while enabling direct intrarack blade-to-blade communication to deliver ultralow chip-to-chip latency. We demonstrate the disaggregated DCN architecture scenarios along with all-optical dimension-programmable N × M spectrum selective Switches (SSS) and an architecture-on-demand (AoD) optical backplane. OPS and OCS complement each other as do TDM and WDM, which can support variable traffic flows. A flat disaggregated DCN architecture is realized by connecting the optical ToR switches directly to either an optical top of cluster switch or the intracluster AoD optical backplane, while clusters are further interconnected to an intercluster AoD for scaling out

Multiplane Orbital Angular Momentum and Wavelength Switch based on Integrated Tunable Vortex Emitters

A multiplane switch architecture exploiting OAM and wavelength domains is characterized in terms of BER, scheduling/reconfiguration latency, and power consumption. Doubling the exploited OAM modes reduces the latency by 42% and the power by 17%

PAM Performance Analysis in Multicast-Enabled Wavelength-Routing Data Centers

Multilevel pulse amplitude modulation (M-PAM) is gaining momentum for high-capacity and power-efficient cloud computing. Compared to the classic on-off keying (OOK) modulation, high-order PAM yields better spectral efficiency but is also more susceptible to physical layer degradation effects. We develop a cross-layer analysis framework to examine the PAM transmission performance in data center network environments supporting both optical multicasting and wavelength routing. Our analysis is conducted on a switch architecture based on an arrayed-waveguide grating (AWG) core and distributed broadcast domains, exhibiting different physical paths, and random, uncontrolled crosstalk noise. Reed-Solomon coding with rate adaptation is incorporated into PAM transceivers to compensate for impairments. Our Monte Carlo simulations point to the significant impact of AWG crosstalk on higher order PAM in wavelength-reuse architectures and the importance of code rate adaptation for signals traversing multiple routing stages. According to our study, 8-PAM offers the highest effective bit rates for signals terminating in one broadcast domain and performs poorly when considering interdomain connectivity. On the other hand, the impairment-induced degradation of interdomain capacity for 4-PAM can be limited to 20.7%, making it better suited for connections spanning two broadcast domains and a crosstalk-rich stage. Our results call for software-defined PAM transceiver designs in support of both modulation order and code rate adaptation

AgileDCN:An Agile Reconfigurable Optical Data Center Network Architecture

This paper presents a detailed examination of a novel data center network (DCN) that can satisfy the high capacity and low latency requirements of modern cloud computing applications. This reconfigurable architecture called AgileDCN uses fast-switching optical components with a centralized control function and workload scheduler. By providing a highly flexible optical network fabric between server racks, very high network efficiencies can be achieved even under imbalanced loading patterns. Our simulation results show that, at high (70%) loads, TCP flow completion times in the AgileDCN are significantly lower than in an equivalent electronic leaf-spine network

Multi-channel collision-free reception for optical interconnects

A multi-channel reception scheme that allows each node to receive an arbitrary set of wavelengths simultaneously (i.e., collision-free) is proposed for optical interconnects. The proposed scheme only needs to use a few receivers and fixed-wavelength filters that are designed based on error-control coding theory. Experiments with up to four channel collision-free reception units are carried out to demonstrate the feasibility of the proposed scheme

Control Plane Hardware Design for Optical Packet Switched Data Centre Networks

Optical packet switching for intra-data centre networks is key to addressing traffic requirements. Photonic integration and wavelength division multiplexing (WDM) can overcome bandwidth limits in switching systems. A promising technology to build a nanosecond-reconfigurable photonic-integrated switch, compatible with WDM, is the semiconductor optical amplifier (SOA). SOAs are typically used as gating elements in a broadcast-and-select (B\&S) configuration, to build an optical crossbar switch. For larger-size switching, a three-stage Clos network, based on crossbar nodes, is a viable architecture. However, the design of the switch control plane, is one of the barriers to packet switching; it should run on packet timescales, which becomes increasingly challenging as line rates get higher. The scheduler, used for the allocation of switch paths, limits control clock speed. To this end, the research contribution was the design of highly parallel hardware schedulers for crossbar and Clos network switches. On a field-programmable gate array (FPGA), the minimum scheduler clock period achieved was 5.0~ns and 5.4~ns, for a 32-port crossbar and Clos switch, respectively. By using parallel path allocation modules, one per Clos node, a minimum clock period of 7.0~ns was achieved, for a 256-port switch. For scheduler application-specific integrated circuit (ASIC) synthesis, this reduces to 2.0~ns; a record result enabling scalable packet switching. Furthermore, the control plane was demonstrated experimentally. Moreover, a cycle-accurate network emulator was developed to evaluate switch performance. Results showed a switch saturation throughput at a traffic load 60\% of capacity, with sub-microsecond packet latency, for a 256-port Clos switch, outperforming state-of-the-art optical packet switches

Cabling and connectors for use on a nuclear stage Final report

Cabling and connectors for use on nuclear stage, environmental and related test