A fully digital feedback control of gate driver for current balancing of parallel connected power devices

Parallel connected power devices such as Insulated Gate Bipolar Transistors (IGBTs) can be used to realize a system with higher current and higher power rating. However, the operation of parallel connected IGBTs is prone to unbalancing due to variation in parameters of the semiconductor devices and asymmetric parallel system. In this paper, feedback control is proposed for peak overshoot minimization as well as current balancing of parallel connected IGBTs. A fully digital feedback control (DFC) is implemented using the universal clock for balanced operation of the two parallel connected IGBTs

An Integrated IGBT Active Gate Driver with Fast Feed-Forward Variable Current

The Insulated-Gate Bipolar Transistor (IGBT) is a hybrid of bipolar and MOSFET transistors. As a consequence, IGBTs can handle higher current typical of bipolar transistors with the ease of control typical of MOSFETs. These characteristics make IGBTs desirable for high power Switch Mode Power Supplies (SMPS). In high power systems such as these, devices must be very reliable, as device failures may result in safety hazards such as fires in addition to the failure of the system. Conventional Gate Driver (CGD) circuits typically design for reliability in these systems by including a resistor between the gate driver and gate of the IGBT. This slows the switching waveforms, reducing stress on the IGBT while sacrificing efficiency. This solution is suboptimal, however, and as such Active Gate Drivers (AGD) have been designed to control voltage and current slopes through the IGBT by modulating the gate signal. AGD circuits found on the market today consist of a combination of an CGD with external components to implement the variable current necessary for protection. This requires a large amount of area on a Printed Circuit Board (PCB), and thus can be costly. Therefore, it can be desirable to integrate the AGD functionality into an on-chip system. In this thesis, an AGD is designed, fabricated and analyzed to show that IGBT gate voltage can be controlled in a manner capable of reducing overvoltage, as well as slowed when desired using an on-chip system. The current provided by this gate driver is controlled by feedback signals indicating the switching state of the device, as well as input bits that determine total output current

Active gate drivers for high-frequency application of SiC MOSFETs

The trend in the development of power converters is focused on efficient systems with high power density, reliability and low cost. The challenges to cover the new power converters requirements are mainly concentered on the use of new switching-device technologies such as silicon carbide MOSFETs (SiC). SiC MOSFETs have better characteristics than their silicon counterparts; they have low conduction resistance, can work at higher switching speeds and can operate at higher temperature and voltage levels. Despite the advantages of SiC transistors, operating at high switching frequencies, with these devices, reveal new challenges. The fast switching speeds of SiC MOSFETs can cause over-voltages and over-currents that lead to electromagnetic interference (EMI) problems. For this reason, gate drivers (GD) development is a fundamental stage in SiC MOSFETs circuitry design. The reduction of the problems at high switching frequencies, thus increasing their performance, will allow to take advantage of these devices and achieve more efficient and high power density systems. This Thesis consists of a study, design and development of active gate drivers (AGDs) aimed to improve the switching performance of SiC MOSFETs applied to high-frequency power converters. Every developed stage regarding the GDs is validated through tests and experimental studies. In addition, the developed GDs are applied to converters for wireless charging systems of electric vehicle batteries. The results show the effectiveness of the proposed GDs and their viability in power converters based on SiC MOSFET devices.La tendencia en el diseño y desarrollo de convertidores de potencia está enfocada en realizar sistemas eficientes con alta densidad de potencia, fiabilidad y bajo costo. Los retos para cubrir esta tendencia están centrados principalmente en el uso de nuevas tecnologías de dispositivos de conmutación tales como, MOSFETs de carburo de silicio (SiC). Los MOSFETs de SiC presentan mejores características que sus homólogos de silicio; tienen baja resistencia de conducción, pueden trabajar a mayores velocidades de conmutación y pueden operar a mayores niveles de temperatura y tensión. A pesar de las ventajas de los transistores de SiC, existen problemas que se manifiestan cuando estos dispositivos operan a altas frecuencias de conmutación. Las rápidas velocidades de conmutación de los MOSFETs de SiC pueden provocar sobre-voltajes y sobre-corrientes que conllevan a problemas de interferencia electromagnética (EMI). Por tal motivo, el desarrollo de controladores de puertas es una etapa fundamental en los MOSFETs de SiC para eliminar los problemas a altas frecuencias de conmutación y aumentar su rendimiento. En consecuencia, aprovechar las ventajas de estos dispositivos y lograr sistemas más eficientes y con alta densidad de potencia. En esta tesis, se realiza un estudio, diseño y desarrollo de controladores activos de puerta para mejorar el rendimiento de conmutación de los MOSFETs de SiC aplicados a convertidores de potencia de alta frecuencia. Los controladores son validados a través de pruebas y estudios experimentales. Además, los controladores de puerta desarrollados son aplicados en convertidores para sistemas de carga inalámbrica de baterías de vehículos eléctricos. Los resultados muestran la importancia de los controladores de compuerta propuestos y su viabilidad en convertidores de potencia basados en carburo de silicio

Fast short-circuit protection for SiC MOSFETs in extreme short-circuit conditions by integrated functions in CMOS-ASIC technology

Wide bandgap power transistors such as SiC MOSFETs and HEMTs GaN push furthermore the classical compromises in power electronics. Briefly, significant gains have been demonstrated: better efficiency, coupled with an increase in power densities offered by the increase in switching frequency. HV SiC MOSFETs have specific features such as a low short-circuit SC withstand time capability compared to Si IGBTs and thinner gate oxide, and a high gate-to-source switching control voltage. The negative bias on the gate at the off-state creates additional stress which reduces the reliability of the SiC MOSFET. The high positive bias on the gate causes a large drain saturation current in the event of a SC. Thus, this technology gives rise to specific needs for ultrafast monitoring and protection. For this reason, the work of this thesis focuses on two studies to overcome these constraints, with the objective of reaching a good performance compromise between “CMS/ASIC-CMOS technological integration level-speed–robustness”. The first one, gathers a set of new solutions allowing a detection of the SC on the switching cycle, based on a conventional switch control architecture with two voltage levels. The second study is more exploratory and is based on a new gate-driver architecture, called multi-level, with low stress level for the SiC MOSFET while maintaining dynamic performances. The manuscript covers firstly the SiC MOSFET environment, (characterization and properties of SC behavior by simulation using PLECS and LTSpice software) and covers secondly a bibliographical study on the Gate drivers. And last, an in-depth study was carried out on SC type I & II (hard switch fault) (Fault under Load) and their respective detection circuits. A test bench, previously carried out in the laboratory, was used to complete and validate the analysis-simulation study and to prepare test stimuli for the design stage of new solutions. Inspired by the Gate charge method that appeared for Si IGBTs and evoked for SiC MOSFETs, this method has therefore been the subject of design, dimensioning and prototyping work, as a reference. This reference allows an HSF type detection in less than 200ns under 400V with 1.2kV components ranging from 80 to 120mOhm. Regarding new rapid and integrated detection methods, the work of this thesis focuses particularly on the design of a CMOS ASIC circuit. For this, the design of an adapted gate driver is essential. An ASIC is designed in X-Fab XT-0.18 SOICMOS technology under Cadence, and then packaged and assembled on a PCB. The PCB is designed for test needs and adaptable to the main bench. The design of the gate driver considered many functions (SC detection, SSD, segmented buffer, an "AMC", ...). From the SC detection point of view, the new integrated monitoring functions concern the VGS time derivative method which is based on a detection by an RC analog shunt circuit on the plateau sequence with two approaches: the first approach is based on a dip detection, i.e. the presence or not of the Miller plateau. The second approach is based on slope detection, i.e. the variability of the input capacitance of the power transistor under SC-HSF compared to normal operation. These methods are compared in the third chapter of the thesis, and demonstrate fault detection times between 40ns and 80ns, and preliminary robustness studies and critical cases are presented. A second new method is partially integrated in the ASIC, was designed. This method is not developed in the manuscript for valorization purposes. In addition to the main study, an exploratory study has focused on a modular architecture for close control at several bias voltage levels taking advantage of SOI isolation and low voltage CMOS transistors to drive SiC MOSFETs and improve their reliability through active and dynamic multi-level selection of switching sequences and on/off states