Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design.

A multilevel dynamic interconnect model was derived for accurate a priori signal integrity estimates. Cross-talk and delay estimations over interconnects in deep submicron technology were analyzed systematically using this model. Good accuracy and excellent time-efficiency were found compared with electromagnetic simulations. We aim to build a dynamic interconnect library with this model to facilitate the interconnect issues for future VLSI design

Atoms-to-Circuits Simulation Investigation of CNT Interconnects for Next Generation CMOS Technology

In this study, we suggest a hierarchical model to investigate the electrical performance of carbon nanotube (CNT)- based interconnects. From the density functional theory, we have obtained important physical parameters, which are used in TCAD simulators to obtain the RC netlists. We then use these RC netlists for the circuit-level simulations to optimize interconnect design in VLSI. Also, we have compared various CNT-based interconnects such as single-walled CNTs, multi-walled CNTs, doped CNTs, and Cu-CNT composites in terms of conductivity, ring oscillator delay, and propagation time delay

A Parameterization Scheme for Lossy Transmission Line Macromodels with Application to High Speed Interconnects in Mobile Devices

We introduce a novel parameterization scheme based on the generalized method of characteristics (MoC) formacromodels of transmission-line structures having a cross section depending on several free geometrical and material parameters. This situation is common in early design stages, when the physical structures still have to be finalized and optimized under signal integrity and electromagnetic compatibility constraints. The topology of the adopted line macromodels has been demonstrated to guarantee excellent accuracy and efficiency. The key factors are propagation delay extraction and rational approximations, which intrinsically lead to a SPICE-compatible macromodel stamp. We introduce a scheme that parameterizes this stamp as a function of geometrical and material parameters such as conductor-width and separation, dielectric thickness, and permettivity. The parameterization is performed via multidimensional interpolation of the residue matrices in the rational approximation of characteristic admittance and propagation operators. A significant advantage of this approach consists of the possibility of efficiently utilizing the MoC methodology in an optimization scheme and eventually helping the design of interconnects.We apply the proposed scheme to flexible printed interconnects that are typically found in portable devices having moving parts. Several validations demonstrate the effectiveness of the approac

Eigenmode-based capacitance calculations with applications in passivation layer design

The design of high-speed metallic interconnects such as microstrips requires the correct characterization of both the conductors and the surrounding dielectric environment, in order to accurately predict their propagation characteristics. A fast boundary integral equation approach is obtained by modeling all materials as equivalent surface charge densities in free space. The capacitive behavior of a finite dielectric environment can then be determined by means of a transformation matrix, relating these charge densities to the boundary value of the electric potential. In this paper, a new calculation method is presented for the important case that the dielectric environment is composed of homogeneous rectangles. The method, based on a surface charge expansion in terms of the Robin eigenfunctions of the considered rectangles, is not only more efficient than traditional methods, but is also more accurate, as shown in some numerical experiments. As an application, the design and behavior of a microstrip passivation layer is treated in some detail

Machine Learning Applied in 2D Parasitic Extraction

With the scale of interconnect number grows to billions, parasitic capacitance extraction speed is an important issue for fast turn-around time for designers. In this thesis, we propose to build a regression model for the input interconnect geometry to predict the parasitic capacitance based on machine learning. A simplification algorithm is proposed to reduce the number of conductors for quicker and easier regression modeling and the regression models can improve by machine learning technique. Experimental results show that the proposed method is significantly faster than existing method and provides satisfactory accuracy

An Algorithmic Framework for Efficient Large-Scale Circuit Simulation Using Exponential Integrators

We propose an efficient algorithmic framework for time domain circuit simulation using exponential integrator. This work addresses several critical issues exposed by previous matrix exponential based circuit simulation research, and makes it capable of simulating stiff nonlinear circuit system at a large scale. In this framework, the system's nonlinearity is treated with exponential Rosenbrock-Euler formulation. The matrix exponential and vector product is computed using invert Krylov subspace method. Our proposed method has several distinguished advantages over conventional formulations (e.g., the well-known backward Euler with Newton-Raphson method). The matrix factorization is performed only for the conductance/resistance matrix G, without being performed for the combinations of the capacitance/inductance matrix C and matrix G, which are used in traditional implicit formulations. Furthermore, due to the explicit nature of our formulation, we do not need to repeat LU decompositions when adjusting the length of time steps for error controls. Our algorithm is better suited to solving tightly coupled post-layout circuits in the pursuit for full-chip simulation. Our experimental results validate the advantages of our framework.Comment: 6 pages; ACM/IEEE DAC 201

Modeling Solder Ball Array Interconnects for Power Module Optimization

PowerSynth is a software platform that can co-optimize power modules utilizing a 2D topology and wire bond interconnects. The novel 3D architectures being proposed at the University of Arkansas utilize solder ball interconnects instead of wire bonds. Therefore, they currently cannot be optimized using PowerSynth. This paper examines methods to accurately model the parasitic inductance of solder balls and ball grid arrays so they may be implemented into software for optimization. Proposed mathematical models are validated against ANSYS Electromagnetics Suite simulations. A comparison of the simulated data shows that mathematical models are well suited for implementation into optimization software platforms. Experimental measurements proved to be inconclusive and necessitate future work