5 research outputs found

    The Impact of Multistability on Hysteresis Arising in Linear and Nonlinear Systems

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    Hysteresis is typically depicted as a looping behaviour in a system's input-output graph. This looping behaviour relates to multiple stable equilibria (that is, multi-stability) in the system. This work examines some necessary stability conditions for linear and nonlinear ordinary differential equations to exhibit hysteresis. Examples and simulations are presented supporting this. Additionally, the shape of hysteresis loops due to different types of multi-stability (e.g. continuum of equilibria or isolated equilibria) are described.Comment: 33 pages, 38 figures, submitted for peer revie

    Enhanced modeling methodology for system-level electrostatic discharge simulation

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    To enable accurate system-level electrostatic discharge (ESD) simulation, models for the equipment under test, the ESD source, and the environment are required. This work presents advanced modeling methods for the ESD source, the victim IC, and other on-board components, most notably the transient voltage suppressor. Kernel regression is used to generate an enhanced quasistatic I-V model of an IC pin, which reflects its dependency on the circuit board’s power delivery network. S-parameter measurements enable the development of a model for an IEC 61000-4-2 ESD source that comprehends the coupling among the ground straps and the ground plane. The transient-voltage-suppressor device is modeled using a behavioral snapback model that shows better convergence in circuit simulation than piece-wise models. Furthermore, ESD-induced soft failures are often caused by the noise coupled between the IC package traces. To help identify this type of failure, a hybrid electromagnetic and circuit simulation approach is demonstrated

    Device Modeling and Circuit Design of Neuromorphic Memory Structures

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    The downscaling of CMOS technology and the benefits gleaned thereof have made it the cornerstone of the semiconductor industry for many years. As the technology reaches its fundamental physical limits, however, CMOS is expected to run out of steam instigating the exploration of new nanoelectronic devices. Memristors have emerged as promising candidates for future computing paradigms, specifically, memory arrays and neuromorphic circuits. Towards this end, this dissertation will explore the use of two memristive devices, namely, Transition Metal Oxide (TMO) devices and Insulator Metal Transition (IMT) devices in constructing neuromorphic circuits. A compact model for TMO devices is first proposed and verified against experimental data. The proposed model, unlike most of the other models present in the literature, leverages the instantaneous resistance of the device as the state variable which facilitates parameter extraction. In addition, a model for the forming voltage of TMO devices is developed and verified against experimental data and Monte Carlo simulations. Impact of the device geometry and material characteristics of the TMO device on the forming voltage is investigated and techniques for reducing the forming voltage are proposed. The use of TMOs in syanptic arrays is then explored and a multi-driver write scheme is proposed that improves their performance. The proposed technique enhances voltage delivery across the selected cells via suppressing the effective line resistance and leakage current paths, thus, improving the performance of the crossbar array. An IMT compact model is also developed and verified against experiemntal data and electro-thermal device simulations. The proposed model describes the device as a memristive system with the temperature being the state variable, thus, capturing the temperature dependent resistive switching of the IMT device in a compact form suitable for SPICE implementation. An IMT based Integrate-And-Fire neuron is then proposed. The IMT neuron leverages the temperature dynamics of the device to deliver the functionality of the neuron. The proposed IMT neuron is more compact than its CMOS counterparts as it alleviates the need for complex CMOS circuitry. Impact of the IMT device parameters on the neuron\u27s performance is then studied and design considerations are provided
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