Optimization and evaluation of variability in the programming window of a flash cell with molecular metal-oxide storage

We report a modeling study of a conceptual nonvolatile memory cell based on inorganic molecular metal-oxide clusters as a storage media embedded in the gate dielectric of a MOSFET. For the purpose of this paper, we developed a multiscale simulation framework that enables the evaluation of variability in the programming window of a flash cell with sub-20-nm gate length. Furthermore, we studied the threshold voltage variability due to random dopant fluctuations and fluctuations in the distribution of the molecular clusters in the cell. The simulation framework and the general conclusions of our work are transferrable to flash cells based on alternative molecules used for a storage media

Analytical modeling of Gate All Around (GAA) MOSFET in nanoscale.

The nano-scale devices face a major issue i.e. Short Channel Effects, as a result of which the performance of the devices degrade. To enhance the performance of such devices, the SCEs should be reduced. This Thesis contributes to enhance the performance of nano-scaled Quadruple gate MOSFET by reducing the SCEs effects. In this work, an accurate analytical sub threshold models has been developed for an Undoped double gate MOSFET considering parabolic approximation of the channel. The Centre (axial) as well as the surface potential model is obtained by solving the 2-D Poisson’s equation. Using two 2-D double gate MOSFETs and then using perimeter weighted sum method the center potential model of the Quadruple gate MOSFET has been developed. The developed Centre potential model is used further to develop the threshold voltage model. The Centre potential model was further applied to estimate the sub threshold drain current and the sub threshold swing of the device. An extensive analysis of the device parameters like the channel thickness, channel width, oxide thickness, channel length etc. on the sub threshold electrical parameters is demonstrated. This gives a highly accurate model which closely matches with the simulations. The models are verified by the simulations obtained from 3-D numerical device simulator Sentaurus from Synopsys

A review of advances in pixel detectors for experiments with high rate and radiation

The Large Hadron Collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog. Phy

Analitical modeling for square gate-all-around MOSFETs

Two analytical models for square Gate All Around (GAA) MOSFETs has been introduced. The first part of this report include a quantum viewpoint and this first work has been published, while the second part approach a classical developed. With the model developed in the first part, it is possible to provide an analytical description of the 2D inversion charge distribution function (ICDF) in square GAA MOSFETs of difeerent sizes and for all the operational regimes. The accuracy of the model is verified by comparing the data with that obtained by means of a 2D numerical simulator that self-consistently solves the Poisson and Schrödinger equations. The expressions presented here are useful to achieve a good description of the physics of these transistors; in particular, of the quantization effects on the inversion charge. The analytical ICDF obtained is used to calculate important parameters from the device compact modeling viewpoint, such as the inversion charge centroid and the gate-to-channel capacitance, which are modeled for different device geometries and biases. The model presented accurately reproduces the simulation results for the devices under study and for different operational regimes. Anyway the second part of this report is focus on square GAA MOSFETs with a classical view point, which have not been analytically described in depth due to their particular geometrical complexity. The analytical description of cylindrical GAA MOSFETs is simpler since the symmetry of the structure around the rotation angle allows a 1D description, accounting just for the radial component. In the case of square GAA MOSFETs other modeling strategies are necessary, as will be shown below. Firstly, a technique to obtain analytical functions which are solutions of the 2D Poisson equation where the charge density in the silicon channel has been calculated, and the total inversion charge is introduced. Among all these functions a simple one for the electric potential in the silicon core of the square GAA MOSFETs was proposed. Secondly, the model introduced has been used to calculate the total inversion charge making use of Gauss's Law. The models obtained are finally validated with simulations data obtained with a 2D simulator developed in our group for Multiple-gate MOSFETs.Universidad de Granada. Departamento de Electrónica y Tecnología de los Computadores. Máster Métodos y Técnicas Avanzadas en Física (MTAF)This work was partially carried out within the framework of Research Projects of Department of Electronic and Computer Technology from the Faculty of Sciences, University of Granada

An analytical model for the inversion charge distribution in square GAA MOSFETs with rounded corners

In this work we introduce an analytical model for square Gate All Around (GAA) MOSFETs with rounded corners including quantum effects. With the model developed it is possible to provide an analytical description of the 2D inversion charge distribution function (ICDF) in devices of different sizes and for all the op erational regimes. The accuracy of the model is verified by comparing with data obtai ned by means of a 2D numerical simulator that self-consistently solves the Poi sson and Schr ̈odinger equations. The expressions presented here are useful to achieve a good d escription of the physics of these transistors; in particular, of the quantization effect s on the inversion charge. The analytical ICDF obtained is used to calculate important par ameters from the device compact modeling viewpoint, such as the inversion charge ce ntroid and the gate-to- channel capacitance, which are modeled for different device g eometries and biases.Universidad de Granada. Departamento de Electrónica y Tecnología de los Computadores. Máster Métodos y Técnicas Avanzadas en Física (MTAF)

Modeling and Simulation of Subthreshold Characteristics of Short-Channel Fully-Depleted Recessed-Source/Drain SOI MOSFETs

Non-conventional metal-oxide-semiconductor (MOS) devices have attracted researchers‟ attention for future ultra-large-scale-integration (ULSI) applications since the channel length of conventional MOS devices approached the physical limit. Among the non-conventional CMOS devices which are currently being pursued for the future ULSI, the fully-depleted (FD) SOI MOSFET is a serious contender as the SOI MOSFETs possess some unique features such as enhanced short-channel effects immunity, low substrate leakage current, and compatibility with the planar CMOS technology. However, due to the ultra-thin source and drain regions, FD SOI MOSFETs possess large series resistance which leads to the poor current drive capability of the device despite having excellent short-channel characteristics. To overcome this large series resistance problem, the source/drain area may be increased by extending S/D either upward or downward. Hence, elevated-source/drain (E-S/D) and recessed-source/drain (Re-S/D) are the two structures which can be used to minimize the series resistance problem. Due to the undesirable issues such as parasitic capacitance, current crowding effects, etc. with E-S/D structure, the Re-S/D structure is a better choice. The FD Re-S/D SOI MOSFET may be an attractive option for sub-45nm regime because of its low parasitic capacitances, reduced series resistance, high drive current, very high switching speed and compatibility with the planar CMOS technology. The present dissertation is to deal with the theoretical modeling and computer-based simulation of the FD SOI MOSFETs in general, and recessed source/drain (Re-S/D) ultra-thin-body (UTB) SOI MOSFETs in particular. The current drive capability of Re-S/D UTB SOI MOSFETs can be further improved by adopting the dual-metal-gate (DMG) structure in place of the conventional single-metal-gate-structure. However, it will be interesting to see how the presence of two metals as gate contact changes the subthreshold characteristics of the device. Hence, the effects of adopting DMG structure on the threshold voltage, subthreshold swing and leakage current of Re-S/D UTB SOI MOSFETs have been studied in this dissertation. Further, high-k dielectric materials are used in ultra-scaled MOS devices in order to cut down the quantum mechanical tunneling of carriers. However, a physically thick gate dielectric causes fringing field induced performance degradation. Therefore, the impact of high-k dielectric materials on subthreshold characteristics of Re-S/D SOI MOSFETs needs to be investigated. In this dissertation, various subthreshold characteristics of the device with high-k gate dielectric and metal gate electrode have been investigated in detail. Moreover, considering the variability problem of threshold voltage in ultra-scaled devices, the presence of a back-gate bias voltage may be useful for ultimate tuning of the threshold voltage and other characteristics. Hence, the impact of back-gate bias on the important subthreshold characteristics such as threshold voltage, subthreshold swing and leakage currents of Re-S/D UTB SOI MOSFETs has been thoroughly analyzed in this dissertation. The validity of the analytical models are verified by comparing model results with the numerical simulation results obtained from ATLAS™, a device simulator from SILVACO Inc