Circuits and Systems for On-Chip RF Chemical Sensors and RF FDD Duplexers

Integrating RF bio-chemical sensors and RF duplexers helps to reduce cost and area in the current applications. Furthermore, new applications can exist based on the large scale integration of these crucial blocks. This dissertation addresses the integration of RF bio-chemical sensors and RF duplexers by proposing these initiatives. A low power integrated LC-oscillator-based broadband dielectric spectroscopy (BDS) system is presented. The real relative permittivity ε’r is measured as a shift in the oscillator frequency using an on-chip frequency-to-digital converter (FDC). The imaginary relative permittivity ε”r increases the losses of the oscillator tank which mandates a higher dc biasing current to preserve the same oscillation amplitude. An amplitude-locked loop (ALL) is used to fix the amplitude and linearize the relation between the oscillator bias current and ε”r. The proposed BDS system employs a sensing oscillator and a reference oscillator where correlated double sampling (CDS) is used to mitigate the impact of flicker noise, temperature variations and frequency drifts. A prototype is implemented in 0.18 µm CMOS process with total chip area of 6.24 mm^2 to operate in 1-6 GHz range using three dual bands LC oscillators. The achieved standard deviation in the air is 2.1 ppm for frequency reading and 110 ppm for current reading. A tunable integrated electrical balanced duplexer (EBD) is presented as a compact alternative to multiple bulky SAW and BAW duplexers in 3G/4G cellular transceivers. A balancing network creates a replica of the transmitter signal for cancellation at the input of a single-ended low noise amplifier (LNA) to isolate the receive path from the transmitter. The proposed passive EBD is based on a cross-connected transformer topology without the need of any extra balun at the antenna side. The duplexer achieves around 50 dB TX-RX isolation within 1.6-2.2 GHz range up to 22 dBm. The cascaded noise figure of the duplexer and LNA is 6.5 dB, and TX insertion loss (TXIL) of the duplexer is about 3.2 dB. The duplexer and LNA are implemented in 0.18 µm CMOS process and occupy an active area of 0.35 mm^2

Ultra high data rate CMOS FEs

The availability of numerous mm-wave frequency bands for wireless communication has motived the exploration of multi-band and multi-mode integrated components and systems in the main stream CMOS technology. This opportunity has faced the RF designer with the transition between schematic and layout. Modeling the performance of circuits after layout and taking into account the parasitic effects resulting from the layout are two issues that are more important and influential at high frequency design. Performaning measurements using on-wafer probing at 60GHz has its own complexities. The very short wave-length of the signals at mm-wave frequencies makes the measurements very sensitiv to the effective length and bending of the interfaces. This paper presents different 60GHz corner blocks, e.g. Low Noise Amplifier, Zero IF mixer, Phase-Locked Loop, A Dual-Mode Mm-Wave Injection-Locked Frequency Divider and an active transformed power amplifiers implemented in CMOS technologies. These results emphasize the feasibility of the realization 60GHZ integrated components and systems in the main stream CMOS technology

Ultra high data rate CMOS front ends

The availability of numerous mm-wave frequency bands for wireless communication has motivated the exploration of multi-band and multi-mode integrated components and systems in the main stream CMOS technology. This opportunity has faced the RF designer with the transition between schematic and layout. Modeling the performance of circuits after layout and taking into account the parasitic effects resulting from the layout are two issues that are more important and influential at high frequency design. Performing measurements using on-wafer probing at 60 GHz has its own complexities. The very short wave-length of the signals at mm-wave frequencies makes the measurements very sensitive to the effective length and bending of the interfaces. This paper presents different 60 GHz corner blocks, e.g. Low Noise Amplifier, Zero IF mixer, Phase-Locked Loop, a Dual-Mode Mm-Wave Injection-Locked Frequency Divider and an active transformed power amplifiers implemented in CMOS technologies. These results emphasize the feasibility of the realization 60 GHZ integrated components and systems in the main stream CMOS technology

Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

Integrated RF oscillators and LO signal generation circuits

This thesis deals with fully integrated LC oscillators and local oscillator (LO) signal generation circuits. In communication systems a good-quality LO signal for up- and down-conversion in transmitters is needed. The LO signal needs to span the required frequency range and have good frequency stability and low phase noise. Furthermore, most modern systems require accurate quadrature (IQ) LO signals. This thesis tackles these challenges by presenting a detailed study of LC oscillators, monolithic elements for good-quality LC resonators, and circuits for IQ-signal generation and for frequency conversion, as well as many experimental circuits. Monolithic coils and variable capacitors are essential, and this thesis deals with good structures of these devices and their proper modeling. As experimental test devices, over forty monolithic inductors and thirty varactors have been implemented, measured and modeled. Actively synthesized reactive elements were studied as replacements for these passive devices. At first glance these circuits show promising characteristics, but closer noise and nonlinearity analysis reveals that these circuits suffer from high noise levels and a small dynamic range. Nine circuit implementations with various actively synthesized variable capacitors were done. Quadrature signal generation can be performed with three different methods, and these are analyzed in the thesis. Frequency conversion circuits are used for alleviating coupling problems or to expand the number of frequency bands covered. The thesis includes an analysis of single-sideband mixing, frequency dividers, and frequency multipliers, which are used to perform the four basic arithmetical operations for the frequency tone. Two design cases are presented. The first one is a single-sideband mixing method for the generation of WiMedia UWB LO-signals, and the second one is a frequency conversion unit for a digital period synthesizer. The last part of the thesis presents five research projects. In the first one a temperature-compensated GaAs MESFET VCO was developed. The second one deals with circuit and device development for an experimental-level BiCMOS process. A cable-modem RF tuner IC using a SiGe process was developed in the third project, and a CMOS flip-chip VCO module in the fourth one. Finally, two frequency synthesizers for UWB radios are presented

A Fully Integrated Multi-Band Multi-Output Synthesizer with Wide-Locking-Range 1/3 Injection Locked Divider Utilizing Self-Injection Technique for Multi-Band Microwave Systems

This dissertation reports the development of a new multi-band multi-output synthesizer, 1/2 dual-injection locked divider, 1/3 injection-locked divider with phase-tuning, and 1/3 injection-locked divider with self-injection using 0.18-micrometer CMOS technology. The synthesizer is used for a multi-band multi-polarization radar system operating in the K- and Ka-band. The synthesizer is a fully integrated concurrent tri-band, tri-output phase-locked loop (PLL) with divide-by-3 injection locked frequency divider (ILFD). A new locking mechanism for the ILFD based on the gain control of the feedback amplifier is utilized to enable tunable and enhanced locking range which facilitates the attainment of stable locking states. The PLL has three concurrent multiband outputs: 3.47-4.313 GHz, 6.94-8.626 GHz and 19.44-21.42-GHz. High second-order harmonic suppression of 62.2 dBc is achieved without using a filter through optimization of the balance between the differential outputs. The proposed technique enables the use of an integer-N architecture for multi-band and microwave systems, while maintaining the benefit of the integer-N architecture; an optimal performance in area and power consumption. The 1/2 dual-ILFD with wide locking range and low-power consumption is analyzed and designed together with a divide-by-2 current mode logic (CML) divider. The 1/2 dual-ILFD enhances the locking range with low-power consumption through optimized load quality factor (QL) and output current amplitude (iOSC) simultaneously. The 1/2 dual-ILFD achieves a locking range of 692 MHz between 7.512 and 8.204 GHz. The new 1/2 dual-ILFD is especially attractive for microwave phase-locked loops and frequency synthesizers requiring low power and wide locking range. The 3.5-GHz divide-by-3 (1/3) ILFD consists of an internal 10.5-GHz Voltage Controlled Oscillator (VCO) functioning as an injection source, 1/3 ILFD core, and output inverter buffer. A phase tuner implemented on an asymmetric inductor is proposed to increase the locking range. The other divide-by-3 ILFD utilizes self-injection technique. The self-injection technique substantially enhances the locking range and phase noise, and reduces the minimum power of the injection signal needed for the 1/3 ILFD. The locking range is increased by 47.8 % and the phase noise is reduced by 14.77 dBc/Hz at 1-MHz offset

Flexible Receivers in CMOS for Wireless Communication

Consumers are pushing for higher data rates to support more services that are introduced in mobile applications. As an example, a few years ago video-on-demand was only accessed through landlines, but today wireless devices are frequently used to stream video. To support this, more flexible network solutions have merged in 4G, introducing new technical problems to the mobile terminal. New techniques are thus needed, and this dissertation explores five different ideas for receiver front-ends, that are cost-efficient and flexible both in performance and operating frequency. All ideas have been implemented in chips fabricated in 65 nm CMOS technology and verified by measurements. Paper I explores a voltage-mode receiver front-end where sub-threshold positive feedback transistors are introduced to increase the linearity in combination with a bootstrapped passive mixer. Paper II builds on the idea of 8-phase harmonic rejection, but simplifies it to a 6-phase solution that can reject noise and interferers at the 3rd order harmonic of the local oscillator frequency. This provides a good trade-off between the traditional quadrature mixer and the 8- phase harmonic rejection mixer. Furthermore, a very compact inductor-less low noise amplifier is introduced. Paper III investigates the use of global negative feedback in a receiver front-end, and also introduces an auxiliary path that can cancel noise from the main path. In paper IV, another global feedback based receiver front-end is designed, but with positive feedback instead of negative. By introducing global positive feedback, the resistance of the transistors in a passive mixer-first receiver front-end can be reduced to achieve a lower noise figure, while still maintaining input matching. Finally, paper V introduces a full receiver chain with a single-ended to differential LNA, current-mode downconversion mixers, and a baseband circuity that merges the functionalities of the transimpedance amplifier, channel-select filter, and analog-to-digital converter into one single power-efficient block

Characterization of process variability and robust optimization of analog circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 161-174).Continuous scaling of CMOS technology has enabled dramatic performance enhancement of CMOS devices and has provided speed, power, and density improvement in both digital and analog circuits. CMOS millimeter-wave applications operating at more than 50GHz frequencies has become viable in sub-100nm CMOS technologies, providing advantages in cost and high density integration compared to other heterogeneous technologies such as SiGe and III-V compound semiconductors. However, as the operating frequency of CMOS circuits increases, it becomes more difficult to obtain sufficiently wide operating ranges for robust operation in essential analog building blocks such as voltage-controlled oscillators (VCOs) and frequency dividers. The fluctuations of circuit parameters caused by the random and systematic variations in key manufacturing steps become more significant in nano-scale technologies. The process variation of circuit performance is quickly becoming one of the main concerns in high performance analog design. In this thesis, we show design and analysis of a VCO and frequency divider operating beyond 70GHz in a 65nm SOI CMOS technology. The VCO and frequency divider employ design techniques enlarging frequency operating ranges to improve the robustness of circuit operation. Circuit performance is measured from a number of die samples to identify the statistical properties of performance variation. A back-propagation of variation (BPV) scheme based on sensitivity analysis of circuit performance is proposed to extract critical circuit parameter variation using statistical measurement results of the frequency divider. We analyze functional failure caused by performance variability, and propose dynamic and static optimization methods to improve parametric yield. An external bias control is utilized to dynamically tune the divider operating range and to compensate for performance variation. A novel time delay model of a differential CML buffer is proposed to functionally approximate the maximum operating frequency of the frequency divider, which dramatically reduces computational cost of parametric yield estimation. The functional approximation enables the optimization of the VCO and frequency divider parametric yield with a reasonable amount of simulation time.by Daihyun Lim.Ph.D

Microelectromechanical Systems for Wireless Radio Front-ends and Integrated Frequency References.

Microelectromechanical systems (MEMS) have great potential in realizing chip-scale integrated devices for energy-efficient analog spectrum processing. This thesis presents the development of a new class of MEMS resonators and filters integrated with CMOS readout circuits for RF front-ends and integrated timing applications. Circuit-level innovations coupled with new device designs allowed for realizing integrated systems with improved performance compared to standalone devices reported in the literature. The thesis is comprised of two major parts. The first part of the thesis is focused on developing integrated MEMS timing devices. Fused silica is explored as a new structural material for fabricating high-Q vibrating micromechanical resonators. A piezoelectric-on-silica MEMS resonator is demonstrated with a high Q of more than 20,000 and good electromechanical coupling. A low phase noise CMOS reference oscillator is implemented using the MEMS resonator as a mechanical frequency reference. Temperature-stable operation of the MEMS oscillator is realized by ovenizing the platform using an integrated heater. In an alternative scheme, the intrinsic temperature sensitivity of MEMS resonators is utilized for temperature sensing, and active compensation for MEMS oscillators is realized by oven-control using a phase-locked loop (PLL). CMOS circuits are implemented for realizing the PLL-based low-power oven-control system. The active compensation technique realizes a MEMS oscillator with an overall frequency drift within +/- 4 ppm across -40 to 70 °C, without the need for calibration. The CMOS PLL circuits for oven-control is demonstrated with near-zero phase noise invasion on the MEMS oscillators. The properties of PLL-based compensation for realizing ultra-stable MEMS frequency references are studied. In the second part of the thesis, RF MEMS devices, including tunable capacitors, high-Q inductors, and ohmic switches, are fabricated using a surface micromachined integrated passive device (IPD) process. Using this process, an integrated ultra-wideband (UWB) filter has been demonstrated, showing low loss and a small form factor. To further address the issue of narrow in-band interferences in UWB communication, a tunable MEMS bandstop filter is integrated with the bandpass filter with more than an octave frequency tuning range. The bandstop filter can be optionally switched off by employing MEMS ohmic switches co-integrated on the same chip.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/109069/1/zzwu_1.pd

Design of Integrated Microwave Frequency Synthesizer-Based Dielectric Sensor Systems

Dielectric sensors have several biomedical and industrial applications where they are used to characterize the permittivity of materials versus frequency. Characterization at RF/microwave frequencies is particularly useful since many chemicals/bio-materials show significant changes in this band. The potential system cost and size reduction possible motivates the development of fully integrated dielectric sensor systems on CMOS with high sensitivity for point-of-care medical diagnosis platforms and for lab-on-chip industrial sensors. Voltage-controlled oscillator (VCO)-based dielectric sensors embed the sensing capacitor within the excitation VCO to allow for self-sustained measurement of the material under test (MUT)-induced frequency shift with simple and precise readout circuits. Despite their advantages, VCO-based sensors have several design challenges. First, low frequency noise and environmental variations limit their sensitivity. Also, these systems usually place the VCO in a frequency synthesizer to control the sample excitation frequency which reduces the resolution of the read-out circuitry. Finally, conventional VCO-based systems utilizing LC oscillators have limited tuning range, and can only characterize the real part of the permittivity of the MUT. This dissertation proposes several ideas to: 1) improve the sensitivity of the system by filtering the low frequency noise and enhance the resolution of the read-out circuitry, 2) improve the tuning range, and 3) enable complex dielectric characterization in VCO/synthesizer-based dielectric spectroscopy systems. The first prototype proposes a highly-sensitive CMOS-based sensing system for permittivity detection and mixture characterization of organic chemicals at microwave frequencies. The system determines permittivity by measuring the frequency difference between two VCOs; a sensor oscillator with an operating frequency that shifts with the change in tank capacitance due to exposure to the MUT and a reference oscillator insensitive to the MUT. This relative measurement approach improves sensor accuracy by tracking frequency drifts due to environmental variations. Embedding the sensor and reference VCOs in a fractional-N phase-locked loop (PLL) frequency synthesizer enables material characterization at a precise frequency and provides an efficient material-induced frequency shift read-out mechanism with a low-complexity bang-bang control loop that adjusts a fractional frequency divider. The majority of the PLL-based sensor system, except for an external fractional frequency divider, is implemented with a 90 nm CMOS prototype that consumes 22 mW when characterizing material near 10 GHz. Material-induced frequency shifts are detected at an accuracy level of 15 ppmrms and binary mixture characterization of organic chemicals yield maximum errors in permittivity of <1.5%. The second prototype proposes a fully-integrated sensing system for wideband complex dielectric detection of MUT. The system utilizes a ring oscillator-based PLL for wide tuning range and precise control of the sensor's excitation frequency. Characterization of both real and imaginary MUT permittivity is achieved by measuring the frequency difference between two VCOs: a sensing oscillator, with a frequency that varies with MUT-induced changes in capacitance and conductance of a delay-cells' sensing capacitor loads, and a MUT-insensitive reference oscillator that is controlled by an amplitude-locked loop (ALL). The fully integrated system is fabricated in 0.18 μm CMOS, and occupies 6.25 mm2 area. When tested with common organic chemicals (ε`r < 30), the system operates between 0.7-6 GHz and achieves 3.7% maximum permittivity error. Characterization is also performed with higher ε`r water-methanol mixtures and phosphate buffered saline (PBS) solutions, with 5.4% maximum permittivity error achieved over a 0.7-4.77 GHz range