Error-power tradeoffs in QCA design

In this work we present an error-power tradeoff study in a Quantum-dot Cellular Automata (QCA) circuit design. Device parameter variation to optimize performance is a very crucial step in the development of a technology. In this work we vary the maximum kink energy of a QCA circuit to perform an error-power tradeoff study in QCA design. We make use of graphical probabilistic models to estimate polarization errors and non-adiabatic energy dissipated in a clocked QCA circuit and demonstrate the tradeoff studies on the basic QCA circuits such as majority gate and inverter. We also show how this study can be used by comparing two single bit adder designs. The study will be of great use to designers and fabrication scientists to choose the most optimum size and spacing of QCA cells to fabricate QCA logic designs

NOVEL SINGLE LAYER FAULT TOLERANCE RCA CONSTRUCTION FOR QCA TECHNOLOGY

Quantum-dot Cellular Automata (QCA) technology has become a promising and accessible candidate that can be used for digital circuits implementation at Nanoscale, but the circuit design in the QCA technology has been limited due to fabrication high-defect rate. So, this issue is an interesting research topic in the QCA circuits design. In this study, a novel 3-input Fault Tolerance (FT) Majority Gate (MG) is developed. Accordingly, an efficient 1-bit QCA full adder is developed using the developed 3-input MG. Then, a new 4-bit FT QCA Ripple Carry Adder (RCA) is developed based on the proposed 1-bit FT QCA FA. The developed circuits are implemented in the QCADesigner tool version 2.0.3. The results indicate that the developed QCA circuits provide advantages compared to other QCA circuits in terms of double and single cell missing defect, area and delay time

Design of Efficient Full Adder in Quantum-Dot Cellular Automata

Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches

Quantum-dot Cellular Automata: Review Paper

Quantum-dot Cellular Automata (QCA) is one of the most important discoveries that will be the successful alternative for CMOS technology in the near future. An important feature of this technique, which has attracted the attention of many researchers, is that it is characterized by its low energy consumption, high speed and small size compared with CMOS.  Inverter and majority gate are the basic building blocks for QCA circuits where it can design the most logical circuit using these gates with help of QCA wire. Due to the lack of availability of review papers, this paper will be a destination for many people who are interested in the QCA field and to know how it works and why it had taken lots of attention recentl

Modeling QCA defects at molecular-level in combinational circuits

This paper analyzes the deposition defects in devices and circuits made of Quantum-dot Cellular Automata (QCA) for molecular implementation. Differently from metal-based QCA, in this type of implementation a defect may occur due to the erroneous deposition of cells (made of molecules) on a substrate, i.e. no cell, or an additional cell is placed either near, or within the layout configuration of a QCA device. The effects of an erroneous cell deposition defect are analyzed by considering the induced functional faults for different QCA devices, such as the majority voter, the inverter and various wire configurations (straight, L-shape, coplanar crossing and fanout). Extensive simulation results are provided. As an example, testing of an EXOR circuit is analyzed in detail. Index terms: fault model, defect tolerance, QCA, emerging technology.

ANALYSIS AND MODULATION OF MOLECULAR QUANTUM-DOT CELLULAR AUTOMATA (QCA) DEVICES

Field-Coupled nanocomputing (FCN) paradigms offer fundamentally new approaches for digital computing without involving current transistors. Such paradigms perform computations using local field interactions between nanoscale building blocks which are organized with purposes. Among several FCN paradigms currently under active investigation, the Molecular Quantum-dot Cellular Automata (MQCA) is found to be the most promising and its unique features make it attractive as a candidate for post-CMOS nanocomputing. MQCA is based on electrostatic interactions among quantum cells with nanometer scale eliminating the need of charge transportation, hence its energy consumption is significantly decreased. Meanwhile it also possesses the potential of high throughput if efficient pipelining of information propagation is introduced. This could be realized adopting external clock signals which precisely control the adiabatic switching and direction of data flow in MQCA circuits. In this work, in order to model MQCA as electronic devices and analyze its information propagation with clock taken into account, an effective algorithm based on ab-initio simulations and modelling of molecular interactions has been applied in presence of a proposed clock mechanism for MQCA, including the binary wire, the wire bus and the majority voter. The quantitative results generated depict compelling clocked information propagation phenomena of MQCA devices and most importantly, provide crucial feedback for future MQCA experimental implementation

Fault and Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices

This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required hardware redundancy is approximately 15 times that of a non-fault tolerant design. While larger than current FT designs, this architecture allows the use of devices much more likely to fail than silicon CMOS. As part of model development, an improved model is derived for NAND Multiplexing. The model is the first accurate model for small and medium amounts of redundancy. Previous models are extended to account for dependence between the inputs and produce more accurate results