Time-Randomized Wormhole NoCs for Critical Applications

Wormhole-based NoCs (wNoCs) are widely accepted in high-performance domains as the most appropriate solution to interconnect an increasing number of cores in the chip. However, wNoCs suitability in the context of critical real-time applications has not been demonstrated yet. In this article, in the context of probabilistic timing analysis (PTA), we propose a PTA-compatible wNoC design that provides tight time-composable contention bounds. The proposed wNoC design builds on PTA ability to reason in probabilistic terms about hardware events impacting execution time (e.g., wNoC contention), discarding those sequences of events occurring with a negligible low probability. This allows our wNoC design to deliver improved guaranteed performance w.r.t. conventional time-deterministic setups. Our results show that performance guarantees of applications running on top of probabilistic wNoC designs improve by 40% and 93% on average for 4 × 4 and 6 × 6 wNoC setups, respectively.The research leading to these results has received funding from the European Community's Seventh Framework Programme [FP7/2007-2013] under the PROXIMA Project (www.proxima-project.eu), grant agreement no 611085. This work has also been partially supported by the Spanish Ministry of Science and Innovation under grant TIN2015-65316-P and the HiPEAC Network of Excellence. Mladen Slijepcevic is funded by the Obra Social Fundación la Caixa under grant Doctorado \la Caixa" - Severo Ochoa. Carles Hernández is jointly funded by the Spanish Ministry of Economy and Competitiveness (MINECO) and FEDER funds through grant TIN2014-60404-JIN. Jaume Abella has been partially supported by the MINECO under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717.Peer ReviewedPostprint (author's final draft

Topics on modelling and simulation of wireless networking protocols

The use of computer simulation to study complex systems has grown significantly over the past several decades. This is especially true with regard to computer networks, where simulation has become a widespread tool used in academic, commercial and military applications. Computer model representations of communication protocol stacks are used to replicate and predict the behavior of real world counterparts to solve a variety of problems.The performance of simulators, measured in both accuracy of results and run time, is a constant concern to simulation users. The running time for high delity simulation of large-scale mobile ad hoc networks can be prohibitively high. The execution time of propagation e ects calculations for a single transmission alone can grow unmanageable to account for all potential receivers. Discrete event simulators can also su er from excessive generation and processing of events, both due to network size and model complexity. In this thesis, three levels of abstracting the Institute of Electrical and Electronics Engineers (IEEE) 802.11 Request to Send/Clear to Send (RTS/CTS) channel access mechanism are presented. In the process of assessing the abstractions' ability to mitigate runtimecost while retaining comparable results to that of a commercially available simulator, OPNET, the abstractions were found to be better suited to collecting one metric over another.Performance issues aside, simulation is an ideal choice for use in prototyping and developing protocols. The costs of simulation are orders of magnitude smaller than that of network testbeds, especially after factoring in the logistics, maintenance, and space required to test live networks. For instance, Internet Protocol version 6 (IPv6) stateless address autocon guration protocols have yet to be convincingly shown to cope with the dynamic, infrastructure-free environment of Mobile Ad hoc Networks (MANETs). This thesis provides a literature survey of autocon guration schemes designed for MANETs, with particular focus on a stateless autocon guration scheme by Jelger andNoel (SECON 2005). The selected scheme provides globally routable IPv6 pre xes to a MANET attached to the Internet via gateways. Using OPNET simulation, the Jelger-Noel scheme is examined with new cluster mobility models, added gateway mobility, and varied network sizes. Performance of the Jelger-Noel scheme, derived from overhead, autocon gura ion time and pre x stability metrics, was found to be highly dependent on network density, and suggested further re nement before deployment.Finally, in cases where a network testbed is used to test protocols, it is still advantageous to run simulations in parallel. While testbeds can help expose design aws due to code or hardware di erences, discrete event simulation environments can o er extensive debugging capabilities andevent control. The two tools provide independent methods of validating the performance of protocols, as well as providing useful feedback on correct protocol implementation and con guration. This thesis presents the Open Shortest Path First (OSPF) routing protocol and its MANET extensions as candidate protocols to test in simulated and emulated MANETs. The measured OSPF overhead from both environments was used as a benchmark to construct equivalent MANET representations and protocol con guration, made particularly challenging due to the wired nature of the emulation testbed. While attempting to duplicate and validate results of a previous OSPF study, limitations of the simulated implementation of OSPF were revealed.M.S., Electrical Engineering -- Drexel University, 200

Energy-aware synthesis for networks on chip architectures

The Network on Chip (NoC) paradigm was introduced as a scalable communication infrastructure for future System-on-Chip applications. Designing application specific customized communication architectures is critical for obtaining low power, high performance solutions. Two significant design automation problems are the creation of an optimized configuration, given application requirement the implementation of this on-chip network. Automating the design of on-chip networks requires models for estimating area and energy, algorithms to effectively explore the design space and network component libraries and tools to generate the hardware description. Chip architects are faced with managing a wide range of customization options for individual components, routers and topology. As energy is of paramount importance, the effectiveness of any custom NoC generation approach lies in the availability of good energy models to effectively explore the design space. This thesis describes a complete NoC synthesis flow, called NoCGEN, for creating energy-efficient custom NoC architectures. Three major automation problems are addressed: custom topology generation, energy modeling and generation. An iterative algorithm is proposed to generate application specific point-to-point and packet-switched networks. The algorithm explores the design space for efficient topologies using characterized models and a system-level floorplanner for evaluating placement and wire-energy. Prior to our contribution, building an energy model required careful analysis of transistor or gate implementations. To alleviate the burden, an automated linear regression-based methodology is proposed to rapidly extract energy models for many router designs. The resulting models are cycle accurate with low-complexity and found to be within 10% of gate-level energy simulations, and execute several orders of magnitude faster than gate-level simulations. A hardware description of the custom topology is generated using a parameterizable library and custom HDL generator. Fully reusable and scalable network components (switches, crossbars, arbiters, routing algorithms) are described using a template approach and are used to compose arbitrary topologies. A methodology for building and composing routers and topologies using a template engine is described. The entire flow is implemented as several demonstrable extensible tools with powerful visualization functionality. Several experiments are performed to demonstrate the design space exploration capabilities and compare it against a competing min-cut topology generation algorithm