Low-power emerging memristive designs towards secure hardware systems for applications in internet of things

Emerging memristive devices offer enormous advantages for applications such as non-volatile memories and in-memory computing (IMC), but there is a rising interest in using memristive technologies for security applications in the era of internet of things (IoT). In this review article, for achieving secure hardware systems in IoT, low-power design techniques based on emerging memristive technology for hardware security primitives/systems are presented. By reviewing the state-of-the-art in three highlighted memristive application areas, i.e. memristive non-volatile memory, memristive reconfigurable logic computing and memristive artificial intelligent computing, their application-level impacts on the novel implementations of secret key generation, crypto functions and machine learning attacks are explored, respectively. For the low-power security applications in IoT, it is essential to understand how to best realize cryptographic circuitry using memristive circuitries, and to assess the implications of memristive crypto implementations on security and to develop novel computing paradigms that will enhance their security. This review article aims to help researchers to explore security solutions, to analyze new possible threats and to develop corresponding protections for the secure hardware systems based on low-cost memristive circuit designs

Increasing pattern recognition accuracy for chemical sensing by evolutionary based drift compensation

Artificial olfaction systems, which mimic human olfaction by using arrays of gas chemical sensors combined with pattern recognition methods, represent a potentially low-cost tool in many areas of industry such as perfumery, food and drink production, clinical diagnosis, health and safety, environmental monitoring and process control. However, successful applications of these systems are still largely limited to specialized laboratories. Sensor drift, i.e., the lack of a sensor's stability over time, still limits real in dustrial setups. This paper presents and discusses an evolutionary based adaptive drift-correction method designed to work with state-of-the-art classification systems. The proposed approach exploits a cutting-edge evolutionary strategy to iteratively tweak the coefficients of a linear transformation which can transparently correct raw sensors' measures thus mitigating the negative effects of the drift. The method learns the optimal correction strategy without the use of models or other hypotheses on the behavior of the physical chemical sensors

Applications of memristors in conventional analogue electronics

This dissertation presents the steps employed to activate and utilise analogue memristive devices in conventional analogue circuits and beyond. TiO2 memristors are mainly utilised in this study, and their large variability in operation in between similar devices is identified. A specialised memristor characterisation instrument is designed and built to mitigate this issue and to allow access to large numbers of devices at a time. Its performance is quantified against linear resistors, crossbars of linear resistors, stand-alone memristive elements and crossbars of memristors. This platform allows for a wide range of different pulsing algorithms to be applied on individual devices, or on crossbars of memristive elements, and is used throughout this dissertation. Different ways of achieving analogue resistive switching from any device state are presented. Results of these are used to devise a state-of-art biasing parameter finder which automatically extracts pulsing parameters that induce repeatable analogue resistive switching. IV measurements taken during analogue resistive switching are then utilised to model the internal atomic structure of two devices, via fittings by the Simmons tunnelling barrier model. These reveal that voltage pulses modulate a nano-tunnelling gap along a conical shape. Further retention measurements are performed which reveal that under certain conditions, TiO2 memristors become volatile at short time scales. This volatile behaviour is then implemented into a novel SPICE volatile memristor model. These characterisation methods of solid-state devices allowed for inclusion of TiO2 memristors in practical electronic circuits. Firstly, in the context of large analogue resistive crossbars, a crosspoint reading method is analysed and improved via a 3-step technique. Its scaling performance is then quantified via SPICE simulations. Next, the observed volatile dynamics of memristors are exploited in two separate sequence detectors, with applications in neuromorphic engineering. Finally, the memristor as a programmable resistive weight is exploited to synthesise a memristive programmable gain amplifier and a practical memristive automatic gain control circuit.Open Acces

Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

21st Century Nanostructured Materials

Nanostructured materials (NMs) are attracting interest as low-dimensional materials in the high-tech era of the 21st century. Recently, nanomaterials have experienced breakthroughs in synthesis and industrial and biomedical applications. This book presents recent achievements related to NMs such as graphene, carbon nanotubes, plasmonic materials, metal nanowires, metal oxides, nanoparticles, metamaterials, nanofibers, and nanocomposites, along with their physical and chemical aspects. Additionally, the book discusses the potential uses of these nanomaterials in photodetectors, transistors, quantum technology, chemical sensors, energy storage, silk fibroin, composites, drug delivery, tissue engineering, and sustainable agriculture and environmental applications

2022 roadmap on neuromorphic computing and engineering

Modern computation based on von Neumann architecture is now a mature cutting-edge science. In the von Neumann architecture, processing and memory units are implemented as separate blocks interchanging data intensively and continuously. This data transfer is responsible for a large part of the power consumption. The next generation computer technology is expected to solve problems at the exascale with 10$^{18}$ calculations each second. Even though these future computers will be incredibly powerful, if they are based on von Neumann type architectures, they will consume between 20 and 30 megawatts of power and will not have intrinsic physically built-in capabilities to learn or deal with complex data as our brain does. These needs can be addressed by neuromorphic computing systems which are inspired by the biological concepts of the human brain. This new generation of computers has the potential to be used for the storage and processing of large amounts of digital information with much lower power consumption than conventional processors. Among their potential future applications, an important niche is moving the control from data centers to edge devices. The aim of this roadmap is to present a snapshot of the present state of neuromorphic technology and provide an opinion on the challenges and opportunities that the future holds in the major areas of neuromorphic technology, namely materials, devices, neuromorphic circuits, neuromorphic algorithms, applications, and ethics. The roadmap is a collection of perspectives where leading researchers in the neuromorphic community provide their own view about the current state and the future challenges for each research area. We hope that this roadmap will be a useful resource by providing a concise yet comprehensive introduction to readers outside this field, for those who are just entering the field, as well as providing future perspectives for those who are well established in the neuromorphic computing community

AND-형 플래시 메모리 어레이를 활용한 하드웨어 기반 스파이킹 뉴럴 네트워크 구현

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 이종호.Neuromorphic engineering aims to implement a brain-inspired computing architecture as an alternative paradigm to the von Neumann processor. In this work, hardware-based neural networks that enable on-chip training using a thin-film transistor-type AND flash memory array architecture are designed. The synaptic device constituting the array is characterized by a doped p-type body, a gate insulator stack composed of SiO2 / Si3N4 / Al2O3, and a partially curved poly-Si channel. The p-body reduces the circuit burden on the high voltage driver required for both the source and drain lines when changing the synaptic weights. The high-κ material included in the gate insulator stack helps to lower the operating voltage of the device. As the device scales down, the structural characteristics of the device have the potential to increase the efficiency of the memory operation and the immunity to the voltage drop effect that occurs in the bit-lines of the array. In the AND array architecture using fabricated synaptic devices, a pulse scheme for selective memory operation is proposed and verified experimentally. Based on the measured characteristics of the fabricated synaptic devices and arrays, we design two types of hardware-based spiking neural networks (SNNs) according to the learning purpose. First, we propose a hardware-based SNN for unsupervised learning with spiking-timing-dependent plasticity (STDP) learning rule. The designed network does not use the pulses generated by the external circuitry, but the necessary pulses are generated in each spike neuron circuit. In this architecture, the STDP rule is implemented by the effective pulse scheme for using poly-silicon AND arrays. With the proposed pulse scheme and SNN, 91.63% of recognition accuracy is obtained in MNIST handwritten digit pattern learning using 200 output neurons. Second, we propose a hardware-based SNN for supervised learning with a direct feedback alignment (DFA) learning rule. Due to the DFA algorithm, which does not need to have the same synaptic weight in the forward path and backward path, the AND array architecture can be utilized in designing an efficient on-chip training neural network. Pulse schemes suitable for the proposed AND array architecture are also devised to implement the DFA algorithm in neural networks. In the system-level simulation, the recognition accuracy of up to 97.01% is obtained in the MNIST pattern learning task based on the proposed pulse scheme and computing architecture. In addition, we propose and verify the integration fabrication method of the proposed synaptic array and complementary metal-oxide-semiconductor (CMOS) circuits. Here, the CMOS circuits include either an integrate-and-fire circuit or a circuit that can change the width or amplitude of the spike signal. The proposed integration fabrication method has the advantage of reducing the number of masks and steps due to the shared process of the synaptic array and CMOS circuit. The proposed integration fabrication method is significant because it presents a methodology for efficient implantation of hardware-based neural networks as well as verification of excellent compatibility of the proposed synaptic device with CMOS.뉴로모픽 기술은 폰 노이만 프로세서의 대안으로서 두뇌에서 영감을 받은 컴퓨팅 아키텍처를 구현하는 것을 목표로 한다. 이 논문에서는 박막 트랜지스터형 및 플래시 메모리 어레이 아키텍처를 사용하여 온칩 훈련을 가능하게 하는 하드웨어 기반 신경망을 설계한다. 어레이를 구성하는 시냅스 소자는 도핑된 p형 바디, SiO2 / Si3N4 / Al2O3로 구성된 게이트 절연막 스택 및 부분적으로 구부러진 폴리실리콘 채널을 특징으로 한다. 시냅스 소자 구조에 포함된 바디 영역은 시냅스 가중치를 변경할 때 소스 및 드레인 라인 모두에 필요한 고전압 드라이버의 회로 부담을 줄일 수 있다. 또한 게이트 절연막 스택에 포함된 high- κ 물질은 시냅스 소자의 동작 전압을 낮출 수 있다. 시냅스 소자의 크기가 축소됨에 따라 소자의 구조적인 특징은 메모리 동작의 효율성 뿐만 아니라 어레이의 비트 라인에서 발생하는 전압 강하 효과에 대한 내성을 증가시킨다. 우리는 제작된 시냅스 소자를 이용한 AND형 어레이 구조에서 선택적인 메모리 동작을 위한 펄스 방식을 제안하고 실험적으로 검증한다. 이후 제작된 시냅스 소자 및 어레이의 측정된 특성을 기반으로 학습 목적에 따라 2가지 유형의 하드웨어 기반 스파이크 신경망 (SNN)을 설계한다. 먼저 스파이크 시점 의존 가소성 기반 학습 규칙을 이용하여 비지도 학습을 위한 하드웨어 기반 SNN을 제안한다. 설계된 네트워크는 외부 회로에서 펄스를 생성하지 않으며 각 스파이크 뉴런 회로에서 필요한 펄스들이 생성된다. 이러한 네트워크에서 스파이크 시점 의존 가소성 기반 학습 규칙은 폴리실리콘 AND형 어레이를 사용하기 위한 효과적인 펄스 구동 방식을 통해 구현된다. 제안된 펄스 구동 방식과 SNN을 기반으로 200개의 출력 뉴런을 사용하는 MNIST 필기 숫자 패턴 학습에서 91.63 %의 인식 정확도를 얻을 수 있다. 두 번째로, 우리는 직접 피드백 정렬 학습 규칙을 사용하여 지도 학습을 위한 하드웨어 기반 SNN을 제안한다. 순방향 경로와 역방향 경로에서 동일한 시냅스 가중치를 가질 필요가 없는 직접 피드백 정렬 알고리즘으로 인해 AND형 어레이 아키텍처는 효율적인 온칩 훈련 신경망 설계에 활용될 수 있다. AND형 어레이 아키텍처에 적합한 펄스 구동 방식도 신경망에서 직접 피드백 정렬 알고리즘을 구현하기 위해 고안된다. 시스템 수준 시뮬레이션에서 제안된 펄스 구동 방식과 컴퓨팅 아키텍처를 기반으로 하는 MNIST 패턴 학습에서 최대 97.01%의 인식 정확도를 얻을 수 있다. 또한, 우리는 제안된 시냅스 어레이와 CMOS 회로의 집적 공정 과정을 제안하고 이를 검증한다. 제안하는 집적 공정 방법은 시냅스 어레이와 CMOS 회로의 공정 과정을 공유함으로써 마스크와 공정 수를 줄일 수 있는 장점이 있다. 제안된 집적 공정 방법은 제안하는 시냅스 소자와 CMOS와의 우수한 호환성을 검증할 뿐만 아니라, 하드웨어 기반 신경망을 효율적으로 구현할 수 있는 방법론을 제시한다는 점에서 의의를 갖는다.Abstract i Contents iv List of Figures viii List of Tables xxvi 1. Introduction 1 1.1 Neuromorphic computing 1 1.2 Hardware-based spiking neural network 5 1.3 Purpose of research 8 1.4 Dissertation outline 11 2. TFT-type AND flash memory array 12 2.1 Device structure and fabrication 12 2.2 Characteristics of the device 17 2.3 Measurement results as a synaptic device 22 2.4 Measurement results as a synaptic array 33 3. Hardware-based SNN for unsupervised learning 48 3.1 SNN using spike-timing-dependent plasticity (STDP) 48 3.2 Pulse scheme for STDP learning rule 54 3.3 MNIST pattern learning and classification 62 4. Hardware-based SNN for supervised learning 67 4.1 SNN using direct feedback alignment (DFA) 67 4.2 Pulse scheme for DFA learning rule 73 4.3 MNIST pattern learning and classification 81 5. Hardware implementation of neural networks 86 5.1 Integration of a synaptic array and CMOS circuits 86 5.2 Measurement results of a synaptic array 101 5.3 Measurement results of CMOS circuits 115 6. Conclusion 139 Appendix A. Neuron circuits to implement a hardware-based neural network using the STDP learning algorithm and the pulse scheme not including the inhibition pulses 142 Appendix B. Neuron circuits to implement a hardware-based neural network using the STDP learning algorithm and the pulse scheme including the inhibition pulses 158 Bibliography 172 Abstract in Korean 181 List of Publications 183박