Refueling: Preventing wire degradation due to electromigration

Electromigration is a major source of wire and via failure. Refueling undoes EM for bidirectional wires and power/ground grids-some of a chip's most vulnerable wires. Refueling exploits EM's self-healing effect by balancing the amount of current flowing in both directions of a wire. It can significantly extend a wire's lifetime while reducing the chip area devoted to wires.Peer ReviewedPostprint (published version

Opportunistic power reassignment between processor and memory in 3D stacks

The pin count largely determines the cost of a chip package, which is often comparable to the cost of a die. In 3D processor-memory designs, power and ground (P/G) pins can account for the majority of the pins. This is because packages include separate pins for the disjoint processor and memory power delivery networks (PDNs). Supporting separate PDNs and P/G pins for processor and memory is inefficient, as each set has to be provisioned for the worst-case power delivery requirements. In this thesis, we propose to reduce the number of P/G pins of both processor and memory in a 3D design, and dynamically and opportunistically divert some power between the two PDNs on demand. To perform the power transfer, we use a small bidirectional on-chip voltage regulator that connects the two PDNs. Our concept, called Snatch, is effective. It allows the computer to execute code sections with high processor or memory power requirements without having to throttle performance. We evaluate Snatch with simulations of an 8-core multicore stacked with two memory dies. In a set of compute-intensive codes, the processor snatches memory power for 30% of the time on average, speeding-up the codes by up to 23% over advanced turbo-boosting; in memory-intensive codes, the memory snatches processor power. Alternatively, Snatch can reduce the package cost by about 30%

Unreliable Silicon: Circuit through System-Level Techniques for Mitigating the Adverse Effects of Process Variation, Device Degradation and Environmental Conditions.

Designing and manufacturing integrated circuits in advanced, highly-scaled processing technologies that meet stringent specification sets is an increasingly unreliable proposition. Dimensional processing variations, time and stress dependent device degradation and potentially varying environmental conditions exacerbate deviations in performance, power and even functionality of integrated circuits. This work explores a system-level adaptive design philosophy intended to mitigate the power and performance impact of unreliable silicon devices and presents enabling circuits for SRAM variation mitigation and in-situ measurement of device degradation in 130nm and 45nm processing technologies. An adaptation of RAZOR-based DVS designed for on-chip memory power reduction and reliability lifetime improvement enables the elimination of 250 mV of voltage margin in a 1.8V design, with up to 500 mV of reduction when allowing 5% of memory operations to use multiple cycles. A novel PID-controlled dynamic reliability management (DRM) system is presented, allowing user-specified circuit lifetime to be dynamically managed via dynamic voltage and frequency scaling. Peak performance improvement of 20-35% is achievable in typical processing systems by allowing brief periods of elevated voltage operation through the real-time DRM system, while minimizing voltage during non-critical periods of operation to maximize circuit lifetime. A probabilistic analysis of oxide breakdown using the percolation model indicates the need for 1000-2000 integrated in-situ sensors to achieve oxide lifetime prediction error at or under 10%. The conclusions from the oxide analysis are used to guide the design of a series of novel on-chip reliability monitoring circuits for use in a real-time DRM system. A 130nm in-situ oxide breakdown measurement sensor presented is the first published design of an oxide-breakdown oriented circuit and is compatible with standard-cell style automatic “place and route” design styles used in the majority of application specific integrated circuit designs. Measured results show increases in gate oxide leakage of 14-35% after accelerated stress testing. A second generation design of the on-chip oxide degradation sensor is presented that reduces stress mode power consumption by 111,785X over the initial design while providing an ideal 1:1 mapping of gate leakage to output frequency in extracted simulations.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/60701/1/ekarl_1.pd

Dependable Embedded Systems

This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from today’s points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability challenges across different levels starting from the physical level all the way to the system level (cross-layer approaches). The book aims at demonstrating how new hardware/software co-design solution can be proposed to ef-fectively mitigate reliability degradation such as transistor aging, processor variation, temperature effects, soft errors, etc. Provides readers with latest insights into novel, cross-layer methods and models with respect to dependability of embedded systems; Describes cross-layer approaches that can leverage reliability through techniques that are pro-actively designed with respect to techniques at other layers; Explains run-time adaptation and concepts/means of self-organization, in order to achieve error resiliency in complex, future many core systems

Electrokinetic Enhanced Bioremediation of Soils Contaminated with Petroleum Hydrocarbons

Desorption of phenanthrene resulting from hydraulic flow is compared to desorption driven by electroosmotic flow with a similar flow rate. The power required for the hydraulic flow test was compared with the consumed power in the electrokinetics test. A novel approach, anode-cathode-compartment (ACC), was proposed to stabilize pH and distribute nutrients in soil in order to enhance electrokinetic bioremediation of soil contaminated with biodegradable compounds. The ACC technique was applied to investigate electrokinetic bioremediation of soil contaminated with phenanthrene. Mycobacterium pallens sp. was used to degrade phenanthrene. Solar energy was used to generate power for the hybrid technique. Three distinct bacterial strains designated as AC16, SM155, and SB53, were subjected to investigation, including ability to grow in liquid medium at different diesel fuel concentrations, identifying functional genes, and the ability to grow at different temperatures and pH. Electrokinetic bioremediation with ACC technique was conducted to mitigate soil contaminated with diesel fuel. The tests were conducted using the novel bacterial strains AC16, SM155 and SB53. The results showed that, the phenanthrene concentration in effluent samples after desorption by electroosmotic flow was found to be three to four times the concentration after desorption by hydraulic flow. The new ACC technique overcomes the shortcomings of other pH stabilization techniques by stabilizing the pH without the need for pumping or amendments. The use of solar panels as a sole source of power can reduce electricity transmission expenses and eliminate power loss in transmission lines. Diesel degradation in tests conducted with electrokinetic bioremediation was between 20 and 30%

Electrokinetic-enhanced migration of solutes for improved bioremediation in heterogeneous granular porous media

Contaminated land is a global problem. Where it presents an unacceptable risk to receptors such as human health or ecosystems, remediation actions must be taken. Current remediation technologies can be ineffective due to mass transfer limitations. A typical scenario where these limitations control remediation efficacy is a physically heterogeneous aquifer where hydraulic conductivity (K) varies spatially. Under these conditions remediation is limited by solute migration across K boundaries. This thesis couples two remediation technologies, in situ bioremediation and electrokinetics (EK), to overcome the mass transfer limitations presented by physically heterogeneous settings. Bioremediation is the transformation of contaminants into less harmful substances by microorganisms; and EK is the application of a direct current to initiate certain transport processes independent of K. Where bioremediation is limited due to the influence of physical heterogeneity, EK transport processes could be applied to initiate an additional flux of solutes across K boundaries. This thesis investigates the influence of physical heterogeneity on EK migration of an amendment designed to enhance bioremediation. The research presented in this thesis advances the current state of knowledge for EK-BIO applications both at the fundamental level and field-scale using laboratory and desk based studies respectively. Laboratory apparatus was designed and built to accommodate physical heterogeneity, electrokinetic transport of solutes and contaminant biodegradation. Broadly, two types of EK experiment were conducted. Firstly, EK amendment migration under abiotic conditions on different arrangements of physical heterogeneity. Secondly, experiments in the same laboratory setup that introduced contaminant and microbial variables. From these experiments a conceptual framework is developed that describes the influence of physical heterogeneity on the EK transport of an amendment. It relates the spatial change in material properties associated with physical heterogeneity with aspects of EK application, such as the voltage gradient, and observes the implications for amendment transport. For example a layered contrast in material type generated a non-uniform electric field when direct current was applied, this led to non-uniform EK transport of the amendment relative to homogeneous settings. When contaminant and microbial variables were introduced to the experimental setup a greater understanding of EK-BIO applications to physically heterogeneous settings was gained. These experiments highlight and discuss the technical issues applying EK to enhance bioremediation by amendment addition versus contaminant removal by EK induced pore fluid movement. Desk based studies included a review of EK-BIO literature and a sustainability assessment that considered EK-BIO at the field scale. The review summarises the practical aspects of the technology in applications to natural environments. It notes that numerous limitations exist to EK-BIO applications in these settings but that there are many different implementation methods that can mitigate these effects. The sustainability assessment compares EK-BIO with conventional remediation technologies against specific criteria for a complex site contaminated with BTEX and MTBE. EK-BIO compares well to other technologies however characteristics of the site will determine the potential sustainability benefits of applying EK

Analysis of design strategies for RF ESD problems in CMOS circuits

This thesis analyses the design strategies used to protect RF circuits that are implemented in CMOS technologies. It investigates, in detail, the physical mechanisms involved when a ggNMOS structure is exposed to an ESD event and undergoes snapback. The understanding gained is used to understand why the performance of the current RF ESD clamp is poor and suggestions are made as to how the performance of ggNMOS clamps can be improved beyond the current body of knowledge. The ultimate aim is to be able to design effective ESD protection clamps whilst minimising the effect the circuit has on RF I/O signals. A current ggNMOS based RF ESD I/O protection circuit is analysed in detail using a Transmission Line Pulse (TLP) tester. This is shown to be a very effective diagnostic tool by showing many characteristics of the ggNMOS during the triggering and conducting phase of the ESD event and demonstrate deficiencies in the clamp design. The use of a FIB enhances the analysis by allowing the isolation of individual components in the circuit and therefore their analysis using the TLP tester. SPICE simulations are used to provide further commentary on the debate surrounding the specification required of a TLP tester for there to be a good correlation between a TLP test and the industry standard Human Body Model (HBM) ESD test. Finite element simulations are used to probe deeper in to the mechanisms involved when a ggNMOS undergoes snapback especially with regard to the contribution parasitic components within the ggNMOS make to the snapback process. New ggNMOS clamps are proposed which after some modification are shown to work. Some of the finite element experiments are repeated in a 0.18μπ7. process CMOS test chip and a comparison is made between the two sets of results. In the concluding chapter understanding that has been gained from previous chapters is combined with the published body of knowledge to suggest and explain improvements in the design of a ggNMOS for RF and standard applications. These improvements will improve homogeneity of ggNMOS operation thus allowing the device size to be reduced and parasitic loading for a given ESD performance. These techniques can also be used to ensure that the ESD current does not take an unintended path through the chip