Reclaiming the energy of a schedule: models and algorithms

We consider a task graph to be executed on a set of processors. We assume that the mapping is given, say by an ordered list of tasks to execute on each processor, and we aim at optimizing the energy consumption while enforcing a prescribed bound on the execution time. While it is not possible to change the allocation of a task, it is possible to change its speed. Rather than using a local approach such as backfilling, we consider the problem as a whole and study the impact of several speed variation models on its complexity. For continuous speeds, we give a closed-form formula for trees and series-parallel graphs, and we cast the problem into a geometric programming problem for general directed acyclic graphs. We show that the classical dynamic voltage and frequency scaling (DVFS) model with discrete modes leads to a NP-complete problem, even if the modes are regularly distributed (an important particular case in practice, which we analyze as the incremental model). On the contrary, the VDD-hopping model leads to a polynomial solution. Finally, we provide an approximation algorithm for the incremental model, which we extend for the general DVFS model.Comment: A two-page extended abstract of this work appeared as a short presentation in SPAA'2011, while the long version has been accepted for publication in "Concurrency and Computation: Practice and Experience

HAPPE: Human and Application-Driven Frequency Scaling for Processor Power Efficiency

Abstract-Conventional dynamic voltage and frequency scaling techniques use high CPU utilization as a predictor for user dissatisfaction, to which they react by increasing CPU frequency. In this paper, we demonstrate that for many interactive applications, perceived performance is highly dependent upon the particular user and application, and is not linearly related to CPU utilization. This observation reveals an opportunity for reducing power consumption. We propose Human and Application driven frequency scaling for Processor Power Efficiency (HAPPE), an adaptive user-and-application-aware dynamic CPU frequency scaling technique. HAPPE continuously adapts processor frequency and voltage to the learned performance requirement of the current user and application. Adaptation to user requirements is quick and requires minimal effort from the user (typically a handful of key strokes). Once the system has adapted to the user's performance requirements, the user is not required to provide continued feedback but is permitted to provide additional feedback to adjust the control policy to changes in preferences. HAPPE was implemented on a Linux-based laptop and evaluated in 22 hours of controlled user studies. Compared to the default Linux CPU frequency controller, HAPPE reduces the measured system-wide power consumption of CPU-intensive interactive applications by 25 percent on average while maintaining user satisfaction. Index Terms-Power, CPU frequency scaling, user-driven study, mobile systems Ç 1I NTRODUCTION P OWER efficiency has been a major technology driver for battery-powered mobile systems, such as mobile phones, personal digital assistants, MP3 players, and laptops. Power efficiency has also become a new focus for line-powered desktop systems and data centers because of its impact on power dissipation and chip temperature, which affect performance, reliability, and lifetime. Processor power consumption is often a substantial portion of system power consumption in mobile systems Traditional CPU power management approaches can lose sight of an important fact: The ultimate goal of any computer system is to satisfy its users, not to execute a particular number of instructions per second. Although CPU utilization is a good indication of processor performance, the actual perceivable system performance depends on individual users and applications, and user satisfaction is not linearly related to CPU utilization. We conducted a study on 10 users with four interactive applications and found that for some applications, some users are satisfied with system performance when the processor is at the lowest frequency, while other users may not be satisfied even when it operates at the highest frequency. We also found that users may be insensitive to varying processor frequency for one application, but may be very sensitive to such changes for another application. Traditional DVFS policies that consider only CPU utilization or other useroblivious performance metrics are often too pessimistic about user performance requirements, and use a high frequency to satisfy all users, resulting in wasted power. Similar findings were also reported in other studies In this paper, we propose Human and Application driven frequency scaling for Processor Power Efficiency (HAPPE), a CPU DVFS technique that adapts voltage and frequency to the performance requirement of the curren

Design and Analysis of an Adaptive Asynchronous System Architecture for Energy Efficiency

Power has become a critical design parameter for digital CMOS integrated circuits. With performance still garnering much concern, a central idea has emerged: minimizing power consumption while maintaining performance. The use of dynamic voltage scaling (DVS) with parallelism has shown to be an effective way of saving power while maintaining performance. However, the potency of DVS and parallelism in traditional, clocked synchronous systems is limited because of the strict timing requirements such systems must comply with. Delay-insensitive (DI) asynchronous systems have the potential to benefit more from these techniques due to their flexible timing requirements and high modularity. This dissertation presents the design and analysis of a real-time adaptive DVS architecture for paralleled Multi-Threshold NULL Convention Logic (MTNCL) systems. Results show that energy-efficient systems with low area overhead can be created using this approach

Energy-Aware Scheduling for Streaming Applications

Streaming applications have become increasingly important and widespread,with application domains ranging from embedded devices to server systems.Traditionally, researchers have been focusing on improving the performanceof streaming applications to achieve high throughput and low response time.However, increasingly more attention is being shifted topower/performance trade-offbecause power consumption has become a limiting factor on system designas integrated circuits enter the realm of nanometer technology.This work addresses the problem of scheduling a streaming application(represented by a task graph)with the goal of minimizing its energy consumptionwhile satisfying its two quality of service (QoS) requirements,namely, throughput and response time.The available power management mechanisms are dynamic voltage scaling (DVS),which has been shown to be effective in reducing dynamic power consumption, andvary-on/vary-off, which turns processors on and off to save static power consumption.Scheduling algorithms are proposed for different computing platforms (uniprocessor and multiprocessor systems),different characteristics of workload (deterministic and stochastic workload),and different types of task graphs (singleton and general task graphs).Both continuous and discrete processor power models are considered.The highlights are a unified approach for obtaining optimal (or provably close to optimal)uniprocessor DVS schemes for various DVS strategies anda novel multiprocessor scheduling algorithm that exploits the differencebetween the two QoS requirements to perform processor allocation,task mapping, and task speedscheduling simultaneously

Abordagens para reconfiguração de sistemas de tempo real com QoS e restrições de energia e temperatura

Tese (doutorado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Engenharia de Automação e Sistemas, Florianópolis, 2015.Esta tese propõe uma infraestrutura para alocação dinâmica de recursos do processador em sistemas de tempo real com tarefas multi-modais ou não, sob restrições de escalonabilidade, consumo de energia e temperatura. Tal infraestrutura pode ser usada para sistemas de tempo real crítico, não crítico e sistemas embarcados que necessitam de garantia de economia de energia. A alocação dinâmica é modelada como um problema de otimização discreto e contínuo (convexos e lineares po rparte) para os quais foram analisados algoritmos eficientes para resolução do problema.Embora o problema discreto formulado seja NP-Difícil, os outros possuem soluções eficientes conhecidas e as análises numéricas e simulações mostraram que os modelos usados alcançam bons resultados, com baixo custo computacional.Abstract : This thesis proposes a framework for dynamic reconfiguration, value-based processor resource allocation in multi-modal or not real-time applications, under schedulability, energy consumption and temperature constraints. The framework is suitable for critical and soft real-time adaptive embedded systems which need guarantees of energy savings. The dynamic allocation is formulated as a discrete and continuous (convex and piecewise linear) optimization problem for which efficients algorithms were tested. Although the discrete problem is NP-Hard, the others have efficient solution and numerical analysis and simulations have shown that the used algorithms and models achieves very good results, with low computational cost

Tolerisanje grešaka i energetska efikasnost kod sistema za rad u realnom vremenu sa vremenskom redundansom

The concept of real-time systems (RTSs) is presented in the computer science for decades. During that period, the RTSs have evolved from special purpose microcomputer systems for industrial application to various forms of embedded system that are deeply ingrained in wide segments of daily life. The new application domains pose new design requirements and goals to RTSs, which are now often required to provide both fault tolerance and energy efficiency in addition to their main objective to compute and deliver correct results within a specified period of time. There is a fundamental tradeoff between these two additional requirements because fault tolerance techniques use slack time to improve reliability while low energy consumption techniques exploits slack time to increase energy efficiency. The central problem considered in the dissertation is how to optimally distribute the slack time between these techniques. Dynamic voltage scaling (DVS) is known as one of the most effective low-energy technique for RTSs. However, most existing DVS techniques only focus on minimizing energy consumption without taking the fault-tolerant capability of RTSs into account. In order to solve specify problem in this dissertation, a new heuristic-based fault-tolerant dynamic voltage and frequency scaling (FT-DVFS) algorithm is developed. The goal of the proposed algorithm is to minimize the amount of energy consumed by a real-time system under fault tolerance constraints while guaranteeing that all real-time tasks can complete successfully before their deadlines. Basically, the FT-DVFS is a DVS algorithm with integrated response time analysis (RTA) to check both the schedulability and the fault tolerant constraints of real-time task sets. The performances of FT-DVFS algorithm are evaluated by simulation in a custom build simulator. The simulation results are analyzed from three different points of view: the schedulability, the energy consumption, and the fault tolerance. The simulation results show that the proposed algorithm saves a significant amount of energy even with only two frequency/voltage levels, and the savings further increases with the increase of the number of frequency levels. Also, the simulations show that the reduction in power consumption, which can be achieved with FT-DVFS algorithm decreases with the increase of the processor utilization factor (i.e. processor spare time). The simulation results from the fault tolerant point of view show that the higher level of fault tolerance can only be attained through sacrificing a part of savings in power consumption, and vice versa. The proposed heuristic FT-DVFS algorithm is compared with the optimal DVS algorithm. The simulation analysis show that FT-DVFS algorithm achieves near-optimal solutions in very short computation time even for large task sets