Sigref – A Symbolic Bisimulation Tool Box

We present a uniform signature-based approach to compute the most popular bisimulations. Our approach is implemented symbolically using BDDs, which enables the handling of very large transition systems. Signatures for the bisimulations are built up from a few generic building blocks, which naturally correspond to efficient BDD operations. Thus, the definition of an appropriate signature is the key for a rapid development of algorithms for other types of bisimulation. We provide experimental evidence of the viability of this approach by presenting computational results for many bisimulations on real-world instances. The experiments show cases where our framework can handle state spaces efficiently that are far too large to handle for any tool that requires an explicit state space description. This work was partly supported by the German Research Council (DFG) as part of the Transregional Collaborative Research Center “Automatic Verification and Analysis of Complex Systems” (SFB/TR 14 AVACS). See www.avacs.org for more information

Formula dependent model reduction through elimination of invisible transitions for checking fragments of CTL

We present a reduction algorithm which reduces Kripke structures by eliminating transitions from the model which do not affect the visible components of the model. These are exactly the variables contained in the specification formula. The reduction algorithm preserves the truth of special CTL formulae. In contrast to formula-dependent reduction algorithms presented so far, which are mostly computationally expensive, our algorithm needs only one pass through the reachable states of the model. Nevertheless, preliminary results show that models are reduced considerably, which is plausible because, in general, the number of visible components of a reactive system is small compared to the number of internal components

Verification of Complex Real-time Systems using Rewriting Logic

This paper presents a method for model checking dense complex real-time systems. This approach is implemented at the meta level of the Rewriting Logic system Maude. The dense complex real-time system is specified using a syntax which has the semantics of timed automata and the property is specified with the temporal logic TLTL (Timed LTL). The well known timed automata model checkers Kronos and Uppaal only support TCTL model checking (a very limited fragment in the case of Uppaal). Specification of the TLTL property is reduced to LTL and its temporal constraints are captured in a new timed automaton. This timed automaton will be composed with the original timed automaton representing the semantics of the complex real-time system under analysis. Then, the product timed automaton will be abstracted using partition refinement of state space based on strong bi-simulation. The result is an untimed automaton modulo the TLTL property which represents an equivalent finite state system to be model checked using Maude LTL model checking. This approach is successfully tested on industrial designs

Dynamic Partitioning in Linear Relation Analysis. Application to the Verification of Synchronous Programs

We apply linear relation analysis [CH78, HPR97] to the verificationof declarative synchronous programs [Hal98]. In this approach,state partitioning plays an important role: on one hand the precision of the results highly depends on the fineness of the partitioning; on the other hand, a too much detailed partitioning may result in an exponential explosion of the analysis. In this paper we propose to consider very general partitions of the state space and to dynamically select a suitable partitioning according to the property to be proved. The presented approach is quite general and can be applied to other abstract interpretations.Keywords and Phrases: Abstract Interpretation, Partitioning,Linear Relation Analysis, Reactive Systems, Program Verificatio

Third Dutch model checking day, Eindhoven, November 7, 2001 : proceedings

This report contains the preliminary proceedings of the third Dutch Model Checking Day, held on 7th November 2001 at the Technische Universiteit Eindhoven. Model checking is an automatic technique for verifying hardware and software systems. The advance of the research in this area in the past few years has lead to a significant improvement of the model checking tools. Successful applications of model checking have been reported in the verification of a wide variety of systems, like complex sequential circuit designs and communication protocols. An important evidence of the great practical potential of model checking is the development of in-house model checking tools within the major companies from the information and telecommunication industry. The objective of the Model Checking Day was to bring together researchers and practitioners from academia and industry who are interested in model checking. The presentations featured both practical and theoretical advances in the area. This includes new techniques and methodologies, as well as experience with their application in various areas, such as embedded systems, communication protocols, hardware components, production processes, etc. Besides this, the Model Checking Day provided an opportunity to exchange experiences, and to have discussions about new ideas and the latest developments in the area. This proceedings contains contributions related to the presentations on this day, details are given in the table of contents. The Model Checking Day received generous support from the Formal Methods Group of the Technische Universiteit Eindhoven and the research school IPA (Institute for Programming research and Algorithmics). At this point I would like to thank the members of the program committee Dragan Bosnacki (TU/e Computer Science), Leszek Holenderski (Philips Research) and Jeroen Voeten (TU/e Electrical Engineering), and the secretary Elize Russell (TU/e Computer Science) for all their work

Étude et implémentation d'une méthode de transformation des automates temporisés en automates à états finis

Les systèmes à événements discrets (SED) sont des systèmes dont le fonctionnement se traduit par des séquences d'interactions.Les SED peuvent être décrits par leurs séquences possibles d'interactions ou événements. Un SED temps-réel est un SED dont le bon fonctionnement dépend non seulement de comment il interagit avec son environnement mais aussi à quels moments ces interactions se produisent. Le modèle automate temporisé (AT) permet de modéliser convenablement les SED temps-réel.Les ATs, qui utilisent un modèle continu du temps, induisent un espace d'états infini pour le système modélisé. Le modèle d'automates à états finis (AEF) par contre permet de représenter de manière finie l'espace des états d'un SED.Les AEFs se prêtent mieux à l'étude (analyse, test, conception, contrôle...) par des méthodes formelles des SED. Une approche standard pour l'étude des SED temps-réel consiste alors à transformer l'AT modélisant le SED en un AEF équivalent sur lequel on réalise l'étude. Dans ce projet, il s'agissait pour nous d'apporter notre contribution à l'élaboration d'une nouvelle méthode de transformation d'un AT en un AEF équivalent.--Résumé abrégé par UMI