Millimeter-wave Communication and Radar Sensing — Opportunities, Challenges, and Solutions

With the development of communication and radar sensing technology, people are able to seek for a more convenient life and better experiences. The fifth generation (5G) mobile network provides high speed communication and internet services with a data rate up to several gigabit per second (Gbps). In addition, 5G offers great opportunities of emerging applications, for example, manufacture automation with the help of precise wireless sensing. For future communication and sensing systems, increasing capacity and accuracy is desired, which can be realized at millimeter-wave spectrum from 30 GHz to 300 GHz with several tens of GHz available bandwidth. Wavelength reduces at higher frequency, this implies more compact transceivers and antennas, and high sensing accuracy and imaging resolution. Challenges arise with these application opportunities when it comes to realizing prototype or demonstrators in practice. This thesis proposes some of the solutions addressing such challenges in a laboratory environment.High data rate millimeter-wave transmission experiments have been demonstrated with the help of advanced instrumentations. These demonstrations show the potential of transceiver chipsets. On the other hand, the real-time communication demonstrations are limited to either low modulation order signals or low symbol rate transmissions. The reason for that is the lack of commercially available high-speed analog-to-digital converters (ADCs); therefore, conventional digital synchronization methods are difficult to implement in real-time systems at very high data rates. In this thesis, two synchronous baseband receivers are proposed with carrier recovery subsystems which only require low-speed ADCs [A][B].Besides synchronization, high-frequency signal generation is also a challenge in millimeter-wave communications. The frequency divider is a critical component of a millimeter-wave frequency synthesizer. Having both wide locking range and high working frequencies is a challenge. In this thesis, a tunable delay gated ring oscillator topology is proposed for dual-mode operation and bandwidth extension [C]. Millimeter-wave radar offers advantages for high accuracy sensing. Traditional millimeter-wave radar with frequency-modulated continuous-wave (FMCW), or continuous-wave (CW), all have their disadvantages. Typically, the FMCW radar cannot share the spectrum with other FMCW radars.\ua0 With limited bandwidth, the number of FMCW radars that could coexist in the same area is limited. CW radars have a limited ambiguous distance of a wavelength. In this thesis, a phase-modulated radar with micrometer accuracy is presented [D]. It is applicable in a multi-radar scenario without occupying more bandwidth, and its ambiguous distance is also much larger than the CW radar. Orthogonal frequency-division multiplexing (OFDM) radar has similar properties. However, its traditional fast calculation method, fast Fourier transform (FFT), limits its measurement accuracy. In this thesis, an accuracy enhancement technique is introduced to increase the measurement accuracy up to the micrometer level [E]

Frequency Multipliers in SiGe BiCMOS for Local Oscillator Generation in D-band Wireless Transceivers

Communications at millimeter-wave (mm-Wave) have drawn a lot of attention in recent years due to the wide available bandwidth which translates directly to higher data transmission capacity. Generation of the transceivers local oscillation (LO) is critical because many contrasting requirements, i.e. tuning range (TR), phase noise (PN), output power, and level of spurious tones, affect the system performance. Differently from what is commonly pursued at Radio Frequency, LO generation with a PLL embedding a VCO at the desired output frequency is not viable at mm-wave. A more promising approach consists of a PLL in the 10-20GHz range, where silicon VCOs feature the best figure of merit, followed by a frequency multiplier. In this thesis, a frequency multiplication chain is investigated to up-convert an LO signal from X-band to D-band by a multiplication factor of 12. The multiplication is done in steps of 3, 2, and 2. A sextupler chip comprises the tripler and the first doubler and the last doubler stage which upconverts the LO signal from E- to D-band is realized in a separate chip, all in a 55nm SiGe BiCMOS technology. The frequency tripler circuit is based on a novel circuit topology which yields a remarkable improvement on the suppression of the driving signal frequency at the output, compared to conventional designs exploiting transistors in class-C. The active core of the circuit approximates the transfer characteristic of a third-order polynomial that ideally produces only a third-harmonic of the input signal. Implemented in a separate break-out chip and consuming 23mW of DC power, the tripler demonstrates ~40dB suppression of the input signal and its 5th harmonic over 16% fractional bandwidth and robustness to power variation of the driving signal over a 15dB range. Including the E-band doubler, the sextupler chip achieves a peak output power of 1.7dBm at 74.4GHz and remains within 2dB variation from 70GHz to 82GHz, corresponding to 16% fractional BW. In this frequency range, the leakages of all harmonics are suppressed by more than 40dBc. The design of the D-band doubler was aimed at delivering high output power with high efficiency and high conversion gain. Toward this end, the efficiency of a push-push pair was improved by a stacked Colpitts oscillator to boost the power conversion gain by 10dB. Moreover, the common-collector configuration keeps separate the oscillator tank from the load, allowing independent optimization of the harmonic conversion efficiency and the load impedance for maximum power delivery. The measured performance of the test chip demonstrated Pout up to 8dBm at 130GHz with 13dB conversion gain and 6.3% Power Added Efficiency

SiGe-based broadband and high suppression frequency doubler ICs for wireless communications

制度:新 ; 報告番号:甲3419号 ; 学位の種類:博士(工学) ; 授与年月日:2011/9/15 ; 早大学位記番号:新574

Quadrature LC VCO with passive coupling and phase combining network

A circuit and method for generating a signal is disclosed. The circuit includes a set of wide tuning LC tanks, a set of core transistors cross coupled to the set of wide tuning LC tanks, and a combining network coupled to the set of wide tuning LC tanks and the set of core transistors. The combining network further includes a set of inputs connected to the set of wide tuning LC tanks and the set of core transistors, a set of coupling transistors connected to the set of inputs, a set of source inductors connected to the set of coupling transistors, a coupling capacitor connected to the set of source inductors, a load resistor connected to the coupling capacitor. The combining network combines the set of inputs and the signal is delivered to the load resistor as a fourth order harmonic.Board of Regents, University of Texas Syste

A STUDY ON LOW-PHASE-NOISE 77-GHZ CMOS TRANSMITTER FOR FMCW RADAR

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2017. 2. 남상욱.This thesis presents design methodology and experimental verification of a low-phase-noise 77-GHz CMOS FMCW (Frequency Modulated Continuous Wave) radar transmitter. It is quite difficult to design a low-phase-noise signal generator at millimeter-wave frequencies in CMOS because gain of CMOS transistors is extremely low at those frequencies. When using a frequency multiplier, it is relatively advantageous to design a low-phase-noise signal source because a VCO can be designed at lower frequency band where gain of active devices is high. When using multiple stage frequency multipliers to achieve low-phase-noise performance, the operating frequency range can be reduced and DC power consumption can be increased. Therefore, in this thesis, two methods for realizing 77-GHz CMOS low-phase-noise signal source have been proposed. One method is to combine a ×6 frequency multiplier and a 12.8-GHz FMCW signal generator. In this case, a VCO, an injection-locked VCO buffer, a ×3 frequency multiplier (tripler), and a ×2 frequency multiplier (doubler) constituting the 77-GHz signal generator are designed as a four-stage coupled injection-locked oscillator (ILO) chain which is oscillated and injected into the output signal of the preceding stage. The VCO used in the 12.8-GHz PLL (phase locked loop) was designed using linearized transconductance (LiT: Linearized Transconductance) technology to have low phase noise characteristics and was designed to be simpler than the existing LiT VCO using a 3:2 transformer. Since the PLL is designed as the integer-N type, an external frequency modulated triangular reference signal must be injected into the phase frequency detector (PFD) of the PLL to generate the FMCW signal. The fabricated transmitter chip supports FMCW output signals in the 76.81-77.95 GHz band when supplied with the external reference triangular signal from 50.00 to 50.75 MHz. The RF output power is about 8.9 dBm and consumes 116.7 mW of DC power. The measured phase noise is -91.16 dBc/Hz at the 1-MHz offset of the 76.81-GHz carrier frequency, which is the lowest phase noise characteristic of the previously announced 77-GHz CMOS transmitter and transceiver. A transmitter module for 77-GHz radar performance measurement was fabricated by combining the transmitter chip with the on-chip feeder that can solve the millimeter-wave packaging problem. The other is a method of combining a ×28 frequency multiplier and a 2.75-GHz FMCW signal generator. As in the previous method, the VCO, a ×7 multiplier, and two ×2 multipliers constituting the 77-GHz signal generator are each designed as a 4-stage ILO chain. The VCO used in the 2.75-GHz PLL is designed as a class-C type that improves the startup problem to have low-phase-noise characteristics. As in the previous case, an integer-N type PLL is used. The fabricated transmitter chip supports FMCW output signals in the 76.26-78.23 GHz band when supplied with the external reference triangular signal from 42.55 to 43.65 MHz. The RF output power is about -18 dBm and consumes 195.4 mW of DC power. The measured phase noise is -93.64 dBc/Hz at the 1-MHz offset of the 78.13-GHz carrier frequency, which is even lower phase noise characteristic than the ×6 frequency multiplier based transmitter chip.Chapter 1. Introduction 1 1.1 Types and Applications of Automotive Radars 2 1.1 Research Strategy 7 Chapter 2. Frequency and Architecture selection 12 2.1 LiT VCO 14 2.2 Class-C VCO 19 2.3 Injection-Locked Oscillator Chain 24 2.4 Summary 29 Chapter 3. 77-GHz FMCW Radar Transmitter with 12.8-GHz PLL and 6 Frequency Multiplier 30 3.1 Proposed LiT VCO 33 3.2 6 Multiplier and Power Amplifier 40 3.3 Measurement Results 46 3.3.1 LiT VCO Measurement Results 46 3.3.2 77-GHz Transmitter (v1) Measurement Results 49 3.4 Summary 60 Chapter 4. 77-GHz FMCW Radar Transmitter with 2.75-GHz PLL and 28 Frequency Multiplier 62 4.1 Proposed class-C VCO 65 4.2 28 Multiplier and Power Amplifier 73 4.3 Measurement Results 80 4.3.1 Class-C VCO Measurement Results 80 4.3.2 77-GHz Transmitter (v2) Measurement Results 83 4.4 Summary 90 Chapter 5. Conclusion 92 Bibliography 94 Abstract 97Docto

CMOS Signal Synthesizers for Emerging RF-to-Optical Applications

The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers. This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented. The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off. The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space. We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam

Dual-Band Transmitter and Receiver with Bowtie-Antenna in 0.13 μm SiGe BiCMOS for Gas Spectroscopy at 222 - 270 GHz

This paper presents a transmitter (TX) and a receiver (RX) with bowtie-antenna and silicon lens for gas spectroscopy at 222-270 GHz, which are fabricated in IHP’s 0.13 μm SiGe BiCMOS technology. The TX and RX use two integrated local oscillators for 222 – 256 GHz and 250 – 270 GHz, which are switched for dual-band operation. Due to its directivity of about 27 dBi, the single integrated bowtie-antenna with silicon lens enables an EIRP of about 25 dBm for the TX, and therefore a considerably higher EIRP for the 2-band TX compared to previously reported systems. The double sideband noise temperature of the RX is 20,000 K (18.5 dB noise figure) as measured by the Y-factor method. Absorption spectroscopy of gaseous methanol is used as a measure for the performance of the gas spectroscopy system with TX- and RX-modules

Frequency Synthesizers and Oscillator Architectures Based on Multi-Order Harmonic Generation

Frequency synthesizers are essential components for modern wireless and wireline communication systems as they provide the local oscillator signal required to transmit and receive data at very high rates. They are also vital for computing devices and microcontrollers as they generate the clocks required to run all the digital circuitry responsible for the high speed computations. Data rates and clocking speeds are continuously increasing to accommodate for the ever growing demand on data and computational power. This places stringent requirements on the performance metrics of frequency synthesizers. They are required to run at higher speeds, cover a wide range of frequencies, provide a low jitter/phase noise output and consume minimum power and area. In this work, we present new techniques and architectures for implementing high speed frequency synthesizers which fulfill the aforementioned requirements. We propose a new architecture and design approach for the realization of wideband millimeter-wave frequency synthesizers. This architecture uses two-step multi-order harmonic generation of a low frequency phase-locked signal to generate wideband mm-wave frequencies. A prototype of the proposed system is designed and fabricated in 90nm Complementary Metal Oxide Semiconductor (CMOS) technology. Measurement results demonstrated that a very wide tuning range of 5 to 32 GHz can be achieved, which is costly to implement using conventional techniques. Moreover the power consumption per octave resembles that of state-of-the art reports. Next, we propose the N-Push cyclic coupled ring oscillator (CCRO) architecture to implement two high performance oscillators: (1) a wideband N-Push/M-Push CCRO operating from 3.16-12.8GHz implemented by two harmonic generation operations using the availability of different phases from the CCRO, and (2) a 13-25GHz millimeter-wave N-Push CCRO with a low phase noise performance of -118dBc/Hz at 10MHz. The proposed oscillators achieve low phase noise with higher FOM than state of the art work. Finally, we present some improvement techniques applied to the performance of phase locked loops (PLLs). We present an adaptive low pass filtering technique which can reduce the reference spur of integer-N charge-pump based PLLs by around 20dB while maintaining the settling time of the original PLL. Another PLL is presented, which features very low power consumption targeting the Medical Implantable Communication Standard. It operates at 402-405 MHz while consuming 600microW from a 1V supply

Transmitters and receivers in SiGe BiCMOS technology for sensitive gas spectroscopy at 222 - 270 GHz

This paper presents transmitter and receiver components for a gas spectroscopy system. The components are fabricated in IHP's 0.13 μm SiGe BiCMOS technology. Two fractional-N phase-locked loops are used to generate dedicated frequency ramps for the transmitter and receiver and frequency shift keying for the transmitter. The signal-to-noise ratio (SNR) for the absorption line of gaseous methanol (CH 3 OH) at 247.6 GHz is used as measure for the performance of the system. The implemented mixer-first receiver allows a high performance of the system due to its linearity up to an input power of -10 dBm. Using a transmitter-array with an output power of 7 dBm an SNR of 4660 (integration time of 2 ms for each data point) was obtained for the 247.6 GHz absorption line of CH 3 OH at 5 Pa. We have extended our single frequency-band system for 228 - 252 GHz to a 2-band system to cover the range 222 - 270 GHz by combining corresponding two transmitters and receivers with the frequency bands 222 - 256 GHz and 250 - 270 GHz on single transmitter- and receiver-chips. This 2-band operation allows a parallel spectra acquisition and therefore a high flexibility of data acquisition for the two frequency-bands. The 50 GHz bandwidth allows for highly specific and selective gas sensing. © 2019 Author(s)

Dual-Band Transmitter and Receiver With Bowtie-Antenna in 0.13 μm SiGe BiCMOS for Gas Spectroscopy at 222 - 270 GHz

This paper presents a transmitter (TX) and a receiver (RX) with bowtie-antenna and silicon lens for gas spectroscopy at 222-270 GHz, which are fabricated in IHP's 0.13 μm SiGe BiCMOS technology. The TX and RX use two integrated local oscillators for 222 - 256 GHz and 250 - 270 GHz, which are switched for dual-band operation. Due to its directivity of about 27 dBi, the single integrated bowtie-antenna with silicon lens enables an EIRP of about 25 dBm for the TX, and therefore a considerably higher EIRP for the 2-band TX compared to previously reported systems. The double sideband noise temperature of the RX is 20,000 K (18.5 dB noise figure) as measured by the Y-factor method. Absorption spectroscopy of gaseous methanol is used as a measure for the performance of the gas spectroscopy system with TX- and RX-modules