Update - Body of Knowledge (BOK) for Copper Wire Bonds

Copper wire bond technology developments continue to be a subject of technical interest to the NASA (National Aeronautics and Space Administration) NEPP (NASA Electronic Parts and Packaging Program) which funded this update. Based on this new research, additional copper bond wire vulnerabilities were found in the literature - Crevice corrosion, intrinsic degradation of palladium coated copper wire, congregation of palladium near ball bond interface leading to failure, residual aluminum pad metallization impact on device lifetimes, stitch cracking phenomena, package delamination's that have resulted in wire bond failures and device failure due to elemental sulfur. A search of the U.S.A. patent web site found 3 noteworthy patents on the following developments: claim of a certain IMC (Intermetallic Compound) thickness as a mitigation solution to chlorine corrosion; claim of using materials with different pHs to neutralize contaminants in a package containing copper wire bonds; and a discussion on ball shear test threshold values for different applications. In addition, an aerospace contractor of military hardware had a presentation on copper bond wires where it was reported that there was a parametric shift and noise susceptibility of devices with copper bond wires which affected legacy design performance. A review of silver bond wire (another emerging technology) technical papers found that an electromigration failure mechanism was evident in device applications that operate under high current conditions. More studies may need to be performed on a comprehensive basis. Research areas for consideration are suggested, however, these research and or qualification/standard test areas are not all inclusive and should not be construed as the element (s) that delivers any potential copper wire bond solution. A false sense of security may occur, whenever there is a reliance on passing any particular qualification, standard, or test protocol

Assessing Au-Al Wire Bond Reliability Using Integrated Stress Sensors

Wire bond reliability testing typically consists of aging bonds in a high temperature environment for long time periods, and removing samples at intervals to assess bond shear strength and characterize the bond cross sections. In this way, the degradation of the bond can be monitored at discrete time intervals, and it is determined whether the bond will be reliable during the specific service life. This process can be labour and time intensive. An alternative method is reported using an existing test chip that allows for contact resistance measurements and provides signals from piezoresistive integrated CMOS microsensors located around test bond pads. The sensors are sensitive to radial compressive or tensile stresses occurring on the bond pad due to intermetallic formation, oxidation, and crack formation at the bond interface. Two sets of identical test chips are bonded with optimized Au ball bonds and aged for 2000 h at 175 ºC. One set is connected to equipment which monitors signals from the stress sensors and the contact resistance of the bonds. The other set is destructively tested by shear tests and cross sectioning. It is found that the stress sensors are capable of indicating which stage of bond aging is experienced by relating the signal to the relative density of the intermetallic compounds (IMCs) and oxide which form during aging. This research offers a valuable new method for accelerating bond process development. By using the sensors to determine the stage of aging experienced and the magnitude of changes happening to the bond, the initial bond quality and bond reliability can be roughly characterized. A useful application is in comparing large samples of bonds made under varying conditions, and determining relative reliabilities of the bonds. A small sample size is required, as the sensors allow for complete continuous aging histories of individual bonds, which was not previously possible. A new test chip is designed for use in future studies which allows for contact resistance measurement, and provides stress signals for up to 55 bonds. A multiplexer integrated on the chip allows for measurements from one specified bond pad at a time. The chip is also equipped with x and yforce measurements which can be used to monitor bond process, and a resistive temperature detector for temperature measurement. A miniaturized bond aging system is designed to facilitate future works where chips are subject to high temperature storage. A heating element fits over the cavity of a microelectronic package containing the test chip, and allows for precise temperature control, while using less power than a conventional oven, and maintaining a low temperature at electrical connections to the package

Experimental Techniques for Static and Dynamic Analysis of Thick Bonding Wires

Thick bonding wires are used in modern power modules as connectors between integrated circuits, carrying current from one circuit to another. They experience high values of current, which generates heat through Joule heating and can lead to various failure mechanisms. Typically used wire materials in industry are aluminum (Al), copper (Cu), and intermetallic compounds of Cu-Al. They are broadly used because of their strength, high thermal conductivity, and low resistivity. This study reports on the influence of thermal loading on the mechanical behaviour of bonding wires. Experimental techniques are developed and introduced in this thesis to analyze quasi-static and dynamic response of bonding wires 300 µm in diameter. First, an experimental technique is developed to measure the quasi-static displacement of bonding wires carrying DC currents. It is then deployed to measure the displacement, as well as peak temperature, of three types of bonding wires, Al, Cu and Aluminum coated Copper (CuCorAl) to study the response under DC current. Secondly, an experimental technique is established and deployed for modal analysis of bonding wires under thermal loading. Experimental results demonstrate a drop in the natural frequency of bonding wires with increased thermal loads. Moreover, a harmonic analysis technique using thermal excitation is developed and applied to analyze the mode shapes and frequency response of bonding wires. Furthermore, an analytical model and a finite element model are used to analyze static and dynamic responses of bonding wires. Numerical and experimental results are compared in this thesis

Développement de procédés avancés d'encapsulation de composants microélectroniques basés sur les techniques de thermocompression

L'un des grands défis de la recherche et développement est d'optimiser l'ensemble du cycle de fabrication d'un produit microélectronique, depuis sa conception jusqu’à sa tenue mécanique en service. Un objectif essentiel des entreprises était de réduire le temps de cycles d’assemblage afin de minimiser les coûts de production. La phase d’assemblage des composants microélectroniques est l'une des étapes clé qui doit être bien optimisée afin d’atteindre l’objectif de minimisation du temps de cycle. La méthode d'assemblage traditionnelle des puces par refusion (en anglais mass reflow MR) convenait généralement à une fabrication à grand volume, en particulier pour des puces à pas standard d'environ 150 μm. Cependant, la forte demande du marché pour des interconnexions à pas plus fin, pour permettre un nombre d'entrée/sortie (Input/Output : I/O) plus élevé dans un facteur de forme plus petit, a entraîné une transition du processus de la liaison MR conventionnel à l'assemblage par thermocompression (en anglais ThermoCompression Bonding TCB). Bien que le procédé TCB offre un assemblage de plus grande précision et permet l'utilisation des pas d'interconnexion plus fins, il présente également de nouveaux défis. L'un des problèmes majeurs de l'assemblage TCB est qu'il s'agit d'un processus assez long, dans lequel chaque puce doit être passée indépendamment à travers un cycle TCB complet, incluant le chauffage, le maintien de la température et le refroidissement. Cela entraîne une diminution significative de la productivité par rapport au MR. Le débit de production peut être amélioré en réduisant le temps nécessaire pour atteindre les températures de processus requises. Cependant, des variations thermiques peuvent se produire aux interfaces de liaison, entraînant une mauvaise uniformité de température sur la surface de la puce et conduisant à des régions où le point de fusion de la brasure n'est pas atteint. Ainsi, il est extrêmement important de prévoir et contrôler la température réelle à l'interface de liaison afin d’obtenir une bonne uniformité thermique et des joints de brasure sans défaut. C'est dans cette perspective que s'inscrit les travaux menés dans la première partie de la thèse. Le premier objectif de cette étude était donc de déterminer la durée minimum de temps de chauffe nécessaire assurant une uniformité de température optimal et par conséquent des joints de brasure de bonne qualité. Pour atteindre cet objectif, il fallait alors proposer et valider une nouvelle méthodologie pour estimer la température d'interface lors d'un processus TCB. Une évaluation de l'influence de différentes vitesses de chauffe sur la distribution de température à travers la surface de la puce, ainsi que sur la qualité de liaison résultante, a été réalisée à l’aide d’un capteur de type RTD (). Les résultats ont montré que les défauts de brasure observés aux interfaces de liaison peuvent éventuellement être liés à une mauvaise uniformité de température, liée à des vitesses de chauffe élevées. Des variations thermiques acceptables ont été trouvées à une faible vitesse de chauffage de 80°C/s. Par conséquent, pour surmonter les températures de processus élevées et leurs effets néfastes sur la productivité, le développement d'une nouvelle méthode d’assemblage TCB à basse température devient primordiale. Le développement d’une nouvelle méthode de liaison par thermocompression à l'état solide détecteur de température résistif, Resistance Temperature Detector en anglais était donc notre second objectif dans cette étude. Cette méthode est basée sur la création d'une liaison mécanique temporaire initiale au début du processus de packaging (en utilisant une pression à une température inférieure au point de fusion de la brasure). Les joints de iv brasure seront entièrement refondus à la fin du processus de packaging, lorsque les billes de brasure BGA (ball-grid-array) seront brasées au substrat. Cette nouvelle méthode peut surmonter les limitations associées au processus TCB conventionnel, notamment la température élevée, le processus d'assemblage lent et les contraintes mécaniques élevées. Une investigation a été menée pour déterminer les conditions d'assemblage appropriées à appliquer pendant ce processus. Des investigations supplémentaires ont été également menées pour explorer le mécanisme d'assemblage responsable de l’assemblage mécanique temporaire. Les résultats préliminaires de cette méthode sont prometteurs, montrant des joints de brasure de bonne qualité formés en un temps d'assemblage très court (6 secondes) et à des températures bien inférieures au TCB conventionnel (200°C)

Harsh-Environment Packaging for Downhole Gas and Oil Exploration

This research into new packaging materials and methods for elevated temperatures and harsh environment electronics focused on gaining a basic understanding of current state-of-the-art in electronics packaging used in industry today, formulating the thermal-mechanical models of the material interactions and developing test structures to confirm these models. Discussions were initiated with the major General Electric (GE) businesses that currently sell into markets requiring high temperature electronics and packaging. They related the major modes of failure they encounter routinely and the hurdles needed to be overcome in order to improve the temperature specifications of these products. We consulted with our GE business partners about the reliability specifications and investigated specifications and guidelines that from IPC and the SAE body that is currently developing guidelines for electronics package reliability. Following this, a risk analysis was conducted for the program to identify the critical risks which need to be mitigated in order to demonstrate a flex-based packaging approach under these conditions. This process identified metal/polyimide adhesion, via reliability for flex substrates and high temperature interconnect as important technical areas for reliability improvement

High-Performance Packaging Technology for Wide Bandgap Semiconductor Modules

The properties of wide band gap (WBG) semiconductors are beneficial to power electronics applications ranging from consumer electronics and renewable energy to electric vehicles and high-power traction applications like high-speed trains. WBG devices, properly integrated, will allow power electronics systems to be smaller, lighter, operate at higher temperatures, and at higher frequencies than previous generations of Si-based systems. These will contribute to higher efficiency, and therefore, lower lifecycle costs and lower CO2 emissions. Over 20 years have been spent developing WBG materials, low-defect-density wafers, epitaxy, and device fabrication and processing technology. In power electronics applications, devices are normally packaged into large integrated modules with electrical, mechanical and thermal connection to the system and control circuit. The first generations of WBG device have used conventional or existing module designs to allow drop-in replacement of Si devices; this approach limits the potential benefit. To realize the full potential of WBG devices, especially the higher operating temperatures and faster switching frequency, a new generation of packaging design and technology concepts must be widely implemented

Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.M.S.Committee Chair: Prof. Rao R Tummala; Committee Member: Dr. Jack Moon; Committee Member: Dr. P M Ra