Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs

This thesis describes a comprehensive, simulation based scaling study – including device design, performance characterization, and the impact of statistical variability – on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface

RTS amplitudes in decananometer MOSFETs: 3-D simulation study

In this paper we study the amplitudes of random telegraph signals (RTS) associated with the trapping of a single electron in defect states at the Si/SiO/sub 2/ interface of sub-100-nm (decananometer) MOSFETs employing three-dimensional (3-D) "atomistic" simulations. Both continuous doping charge and random discrete dopants in the active region of the MOSFETs are considered in the simulations. The dependence of the RTS amplitudes on the position of the trapped charge in the channel and on device design parameters such as dimensions, oxide thickness and channel doping concentration is studied in detail. The 3-D simulations offer a natural explanation for the large variation in the RTS amplitudes measured experimentally in otherwise identical MOSFETs. The random discrete dopant simulations result in RTS amplitudes several times higher compared to continuous charge simulations. They also produce closer to the experimentally observed distributions of the RTS amplitudes. The results highlight the significant impact of single charge trapping in the next generation decananometer MOSFETs

Quantifying device degradation in live power converters using SSTDR assisted impedance Matrix

pre-printA noninterfering measurement technique designed around spread spectrum time domain reflectometry (SSTDR) has been proposed in this paper to identify the level of aging associated with power semiconductor switches inside a live converter circuit. Power MOSFETs are one of the most age-sensitive components in power converter circuits, and this paper demonstrates how SSTDR can be used to determine the characteristic degradation of the switching MOSFETs used in various power converters. An SSTDR technique was applied to determine the aging in power MOSFETs, while they remained energized in live circuits. In addition, SSTDR was applied to various test nodes of an H-bridge ac-ac converter, and multiple impedance matrices were created based on the measured reflections. An error minimization technique has been developed to locate and determine the origin and amount of aging in this circuit, and this technique provides key information about the level of aging associated to the components of interest. By conducting component level failure analysis, the overall reliability of an H-bridge ac-ac converter has been derived and incorporated in this paper

Simulation of charge-trapping in nano-scale MOSFETs in the presence of random-dopants-induced variability

The growing variability of electrical characteristics is a major issue associated with continuous downscaling of contemporary bulk MOSFETs. In addition, the operating conditions brought about by these same scaling trends have pushed MOSFET degradation mechanisms such as Bias Temperature Instability (BTI) to the forefront as a critical reliability threat. This thesis investigates the impact of this ageing phenomena, in conjunction with device variability, on key MOSFET electrical parameters. A three-dimensional drift-diffusion approximation is adopted as the simulation approach in this work, with random dopant fluctuations—the dominant source of statistical variability—included in the simulations. The testbed device is a realistic 35 nm physical gate length n-channel conventional bulk MOSFET. 1000 microscopically different implementations of the transistor are simulated and subjected to charge-trapping at the oxide interface. The statistical simulations reveal relatively rare but very large threshold voltage shifts, with magnitudes over 3 times than that predicted by the conventional theoretical approach. The physical origin of this effect is investigated in terms of the electrostatic influences of the random dopants and trapped charges on the channel electron concentration. Simulations with progressively increased trapped charge densities—emulating the characteristic condition of BTI degradation—result in further variability of the threshold voltage distribution. Weak correlations of the order of 10-2 are found between the pre-degradation threshold voltage and post-degradation threshold voltage shift distributions. The importance of accounting for random dopant fluctuations in the simulations is emphasised in order to obtain qualitative agreement between simulation results and published experimental measurements. Finally, the information gained from these device-level physical simulations is integrated into statistical compact models, making the information available to circuit designers

Piikarbidi-MOSFET:n kiihdytetty ikäännyttäminen ja prognostiikka

The reliability investigations in power semiconductor components have traditionally concentrated on statistical analysis of the failure data in order to set regular maintenance intervals to prevent failures in the field. A more recent discipline, prognostics, in turn attempts to evaluate the current state-of-health of the device online and to predict the remaining useful life by interpreting signals of degradation. The utilization of prognostics is valuable to businesses as it enables addressing the maintenance only to the products close to failure. In this thesis we studied prognostics from the physics-based perspective in two types of silicon carbide power MOSFETs, in 11 samples in total. The components were aged in a power cycling test system to produce data of the selected failure precursor, drain-source on-state resistance. For the prognostic analysis we developed a kernel\hyp{}smoothing\hyp{}based particle filter and applied it to joint state\hyp{}parameter estimation of a selected sample. The analysis results indicated satisfactory performance regarding the estimation of the states and the parameters but revealed significant deficiencies in the prediction performance of the remaining useful life. Although the work mainly focuses on studying the power MOSFET as single component it is important to observe it also as a part of a larger entity. Therefore, at the end of the work we propose design principles for a new test system where the power MOSFET operates in a DC-DC converter. The derived precepts are based on the insight of reliability data analysis and prognostics gained during the study.Tehopuolijohdekomponenttien luotettavuustutkimukset ovat perinteisesti keskittyneet vikadatan tilastolliseen analyysiin säännöllisten huoltovälien asettamiseksi, joilla ehkäistään kentällä tapahtuvia vikaantumisia. Prognostiikka on uudempi tiedonala, joka puolestaan pyrkii määrittämään laitteen käytönaikaisen terveydentilan ja ennustamaan jäljellä olevan elinajan tulkitsemalla signaaleja huononemista. Prognostiikan hyödyntäminen on arvokasta liiketoiminnalle, sillä se mahdollistaa huollon kohdistamisen ainostaan niille laitteille, jotka ovat lähellä vikaantumista. Tässä diplomityössä tutkimme prognostiikkaa fysiikkaan pohjautuvasta näkökulmasta kahdessa erityyppisessä piikarbiditeho-MOSFET:ssa, kokonaisuudessaan 11 näytteessä. Komponentit ikäännytettiin tehosyklaustestissä nielulähdepäälläoloresistanssidatan keräämiseksi, joka valittiin vikaantumisindikaattoriksi. Prognostista analyysia varten kehitimme ydinsilotukseen perustuvan partikkelisuodattimen, jota sovelsimme yhdistetyyn tilaparametriestimointiin valitussa näytteessä. Analyysin tulokset osoittivat tyydyttävää suorituskykyä tilan ja parametrien estimointissa mutta paljastivat merkittäviä puutteita jäljellä olevan eliniän ennustamisessa. Vaikka työ pääosin keskittyy teho-MOSFET:n tutkimiseen yksittäisenä komponenttina, on tärkeä huomioda se myös osana suurempaa kokonaisuutta. Tämän vuoksi työn lopussa esitetään suunnitteluperiaatteita uutta testausjärjestelmää varten, jossa teho-MOSFET toimii DC-DC -muuntimessa. Johdetut ohjenuorat pohjaavat työn aikana kertyneelle ymmärrykselle luotettavuusdatan analysoinnista ja prognostiikasta