Thermosonic flip chip interconnection using electroplated copper column arrays

Published versio

Evaluation of 3D Plus Packaging Test Structures for NASA Goddard Space Flight Center

Environmental tests were performed on packaging test structures designed and manufactured for ESA and CNES by 3D PLus ELectronics. The design provided circuit elements that acted as thermal, mechanical and moisture sensors. Other design features showed the compatibility of the packaging with chip passives, bare electronic dice and plastic encapsulated microcircuits packaged together in an innovative, stacked multichip module. The NASA GSFC testing augmented long duration testing on the same units carried out by ESA and CNES. The NASA portion demonstrated packaging stability over temperature, in moisture, with voltage stress, in shock and in vibration environments

The Development and Packaging of a High-Density, Three-Phase, Silicon Carbide (SiC) Motor Drive

Technology advances within the power electronics field are resulting in systems characterized by higher operating efficiencies, reduced footprint, minimal form factor, and decreasing mass. In particular, these attributes and characteristics are being inserted into numerous consumer applications, such as light-emitting diode lighting, compact fluorescent lighting, smart phones, and tablet PCs, to industrial applications that include hybrid, electric, and plug-in electric vehicles and more electric aircraft. To achieve the increase in energy efficiency and significant reduction in size and mass of these systems, power semiconductor device manufacturers are developing silicon carbide (SiC) semiconductor technology. In this dissertation, the author discusses the design, development, packaging, and fabrication of the world\u27s first multichip power module (MCPM) that integrates SiC power transistors with silicon-on-insulator (SOI) integrated circuits. The fabricated MCPM prototype is a 4 kW, three-phase inverter that operates at temperatures in excess of 250 °C. The integration of high-temperature metal-oxide semiconductor (HTMOS) SOI bare die control components with SiC power JFET bare die into a single compact module are presented in this work. The high-temperature operation of SiC switches allows for increased power density over silicon electronics by an order of magnitude, leading to highly miniaturized power converters. This dissertation is organized into a compilation of publications written by the author over the course of his Ph.D. work. The work presented throughout these publications covers the challenges associated with power electronics miniaturization and packaging including high-power density, high-temperature, and high-efficiency operation of the power electronic system under study

A Low Temperature Co-fired Ceramic (LTCC) Interposer Based Three-Dimensional Stacked Wire Bondless Power Module

The objective of this dissertation research is to develop a low temperature co-fired ceramic (LTCC) interposer-based module-level 3-D wire bondless stacked power module. As part of the dissertation work, the 3-D wire bondless stack is designed, simulated, fabricated and characterized. The 3-D wire bondless stack is realized with two stand-alone power modules in a half-bridge configuration. Each stand-alone power module consists of two 1200 V 25 A silicon insulated-gate bipolar transistor (IGBT) devices in parallel and two 1200 V 20 A Schottky barrier diodes (SBD) in an antiparallel configuration. A novel interconnection scheme with conductive clamps and a spring loaded LTCC interposer is introduced to establish electrical connection between the stand-alone power modules to connect them in series to realize a half-bridge stack. Process development to fabricate the LTCC based 3-D stack is performed. In traditional power modules, wire bonds are used as a top side interconnections that introduce additional parasitic inductance in the current conduction path and prone to failure mechanism under high thermomechanical stresses. The loop inductance of the proposed 3-D half-bridge module exhibits 71% lower parasitic inductance compared to a wire bonded module. The 3-D stack exhibits better switching performance compared to the wire bonded counterpart. The measurement results for the 3-D stack shows 30% decrease in current overshoot at turn-on and 43% voltage overshoot at turn-off compared to the wire bonded module. Through measurements, it has been shown that the conducted noise reduces by 20 dB in the frequency range 20-30 MHz for the 3-D stack compared to the wire bonded counterpart. A simulation methodology using co-simulation techniques using ANSYS EM software tools is developed to predict EMI of a power module. Hardware verification of the proposed simulation methodology is performed to validate the co-simulation technique. The correlation coefficient between the measurement and simulation is found to be 0.73. It is shown that 53% of the variability in the simulation can be explained by the simulated result. Moreover, the simulated and measured amplitudes of the EMI spectrum closely match with each other with some variations due to round-off errors due to the FFT conversion

Methods For Fabricating Three-dimensional All Organic Interconnect Structures

The present invention includes methods for making liquid crystalline polymer (LCP) interconnect structures using a high temperature and low temperature single sided liquid crystalline polymer LCP where both the high and low temperature LCP are drilled to form a z-axis connection. The single sided conductive layer is a bus layer to form z axis conductive stud within the high and low temperature LCP, followed by a metallic capping layer of the stud that serves as the bonding metal between the conductive interconnects to form the z-axis connection. High and low temperature LCP layers are etched or built up to form circuit patterns and subsequently bonded together to form final multilayer circuit pattern where the low temperature LCP melts to form both dielectric to dielectric bond to high temperature LCP circuit layer, and dielectric to conductive bond, whereas metal to metal bonding occurs with high temperature metal capping layer bonding to conductive metal layer.Georgia Tech Research Corporatio

Laser Tabbed Die: A Repairable, High-Speed Die-Interconnection Technology. 1994 Ldrd Final Report 93-Sr-089

A unique technology for multichip module production is presented. The technology, called Laser Tabbed Die (L-TAB), consists of a method for forming surface-mount-type {open_quotes}gull wing{close_quotes} interconnects on bare dice. The dice are temporarily bonded to a sacrificial substrate which has a polymer thin film coated onto it. The gull wings are formed on the side of the die with a direct-write laser patterning process which allows vertical as well as horizontal image formation. Using the laser patterning system, trenches are formed in a positive electrodeposited photoresist (EDPR) which is plated onto a metal seed layer, allowing copper to be electroplated through the resultant mask. After stripping the resist and the metal seed layer, the polymer film on the substrate is dissolved, releasing the chip with the {open_quotes}gull wings{close_quotes} intact. The chips are then bonded onto a circuit board or permanent substrate with solder or conductive adhesive

Simulation and fabrication of an interposer for electrical testing of fine-pitch wafer-level packages

Master'sMASTER OF ENGINEERIN

Miniaturizing microvias for multi-chip modules

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 63-64).Electronics packaging is continually migrating toward denser packaging. This encompasses a push toward multilevel die, denser metallization, and smaller microvias. In this thesis we investigate the miniaturization of laser-drilled microvias in polyimide dielectric for chips-first multi-chip module (MCM) technology. The challenge is to produce increasingly smaller microvias and package more microvias into a given area without sacrificing electrical performance. Principally, this means a microvia must maintain certain minimum electrical resistance and mechanical adhesion to the conducting layers. The thesis encompasses the following research: 1. Investigating the state of the art in laser-drilled polyimide microvias. 2. Designing and fabricating test structures with microvias, in which the state of the art is pushed in microvia size and/or aspect ratio. 3. Measuring the contact resistances of laser-drilled microvias in a Kelvin structure configuration. 4. Developing finite element models of Kelvin structures to estimate the contact resistance of miniature microvias.The experimental results of this thesis prove that microvias with approximately 19 pm diameter and 10 mQ contact resistance can be reliably fabricated for chips-first MCM technology.by Paul Gerard Puskarich.M.Eng

Modeling and analysis of semiconductor manufacturing processes using petri nets

This thesis addresses the issues in modeling and analysis of multichip module (MCM) manufacturing processes using Petri nets. Building such graphical and mathematical models is a crucial step to understand MCM technologies and to enhance their application scope. In this thesis, the application of Petri nets is presented with top-down and bottom-up approaches. The theory of Petri nets is summarized with its basic notations and properties at first. After that, the capability of calculating and analyzing Petri nets with deterministic timing information is extended to meet the requirements of the MCM models. Then, using top-down refining and system decomposition, MCM models are built from an abstract point to concrete systems with timing information. In this process, reduction theory based on a multiple-input-single-output modules for deterministic Petri nets is applied to analyze the cycle time of Petri net models. Besides, this thesis is of significance in its use of the reduction theory which is derived for timed marked graphs - an important class of Petri nets