Interactive Educational Tool for Memory Testing

Memories are one of the most important components in digital systems like SoCs. The high density of their cell array makes memories extremely vulnerable to physical defects. Hence, memory testing and Design-for-Test became one of the crucial tasks in the design of complex and heterogeneous SoCs. Politecnico di Torino and the Institute of Informatics have a wide experience in the field of RAM testing (i.e., automatic march test generation, fault simulators, memory BIST generators etc.). This work is a tentative to put the joint experience of our research groups in developing an interactive educational tool for the students that should introduce standard and well-known methods of memory testing based on BIST. The MemBIST Java Applet and the March Test Generator were two individual tools designed and implemented at the two mentioned institutions. They were merged into one tool in order to facilitate its usage also by the professional

Memory Testing on SGI/MIPS Architecture

Moje bakalářská práce se zabývá zprovozněním a vytvořením vlastních testů paměti na grafických stanicích SGI O2, což sebou přináší seznámení se s architekturou procesorů MIPS a pokouší se najít ideální prostředí pro provádění těchto testů. S tím úzce souvisí hledání vhodného způsobu spouštění a překladu aplikací pro stanice SGI O2, kde se zabývá také využitím křížových kompilátorů.Work is engaged in making solution for creating own memory tests on graphical station SGI O2. This thesis produces work on MIPS processor architecture and it try to find the ideal environments for testing memory and with it is nearly related looking for chances of start and compile application for SGI O2. Part of my thesis is also target using cross-compilers, for effective and useful work with program for other architecture.

Interactive Educational Tool for Memory Testing

Memories are one of the most important components in digital systems like SoCs. The high density of their cell array makes memories extremely vulnerable to physical defects. Hence, memory testing and Design-for-Test became one of the crucial tasks in the design of complex and heterogeneous SoCs. Politecnico di Torino and the Institute of Informatics have a wide experience in the field of RAM testing (i.e., automatic march test generation, fault simulators, memory BIST generators etc.). This work is a tentative to put the joint experience of our research groups in developing an interactive educational tool for the students that should introduce standard and well-known methods of memory testing based on BIST. The MemBIST Java Applet and the March Test Generator were two individual tools designed and implemented at the two mentioned institutions. They were merged into one tool in order to facilitate its usage also by the professionals

How Hard is Weak-Memory Testing?

Weak-memory models are standard formal specifications of concurrency across hardware, programming languages, and distributed systems. A fundamental computational problem is consistency testing: is the observed execution of a concurrent program in alignment with the specification of the underlying system? The problem has been studied extensively across Sequential Consistency (SC) and weak memory, and proven to be NP-complete when some aspect of the input (e.g., number of threads/memory locations) is unbounded. This unboundedness has left a natural question open: are there efficient parameterized algorithms for testing? The main contribution of this paper is a deep hardness result for consistency testing under many popular weak-memory models: the problem remains NP-complete even in its bounded setting, where candidate executions contain a bounded number of threads, memory locations, and values. This hardness spreads across several Release-Acquire variants of C11, a popular variant of its Relaxed fragment, popular Causal Consistency models, and the POWER architecture. To our knowledge, this is the first result that fully exposes the hardness of weak-memory testing and proves that the problem admits no parameterization under standard input parameters. It also yields a computational separation of these models from SC, x86-TSO, PSO, and Relaxed, for which bounded consistency testing is either known (for SC), or shown here (for the rest), to be in polynomial time

Modified March C - Algorithm for Embedded Memory Testing

March algorithms are known for memory testing because March-based tests are all simple and possess good fault coverage hence they are the dominant test algorithms implemented in most modern memory BIST. The proposed march algorithm is modified march c- algorithm which uses concurrent technique. Using this modified march c- algorithm the complexity is reduced to 8n as well as the test time is reduced greatly. Because of concurrency in testing the sequences the test results were observed in less time than the traditional March tests. This technique is applied for a memory of size   256x8 and can be extended to any memory size.DOI:http://dx.doi.org/10.11591/ijece.v2i5.158

Effective Test Pattern Generation using LFSR for Memory Testing

Volume 2 Issue 3 (March 2014

Brief targeted memory reactivation during the awake state enhances memory stability and benefits the weakest memories.

Reactivation of representations corresponding to recent experience is thought to be a critical mechanism supporting long-term memory stabilization. Targeted memory reactivation, or the re-exposure of recently learned cues, seeks to induce reactivation and has been shown to benefit later memory when it takes place during sleep. However, despite recent evidence for endogenous reactivation during post-encoding awake periods, less work has addressed whether awake targeted memory reactivation modulates memory. Here, we found that brief (50 ms) visual stimulus re-exposure during a repetitive foil task enhanced the stability of cued versus uncued associations in memory. The extent of external or task-oriented attention prior to re-exposure was inversely related to cueing benefits, suggesting that an internally-orientated state may be most permissible to reactivation. Critically, cueing-related memory benefits were greatest in participants without explicit recognition of cued items and remained reliable when only considering associations not recognized as cued, suggesting that explicit cue-triggered retrieval processes did not drive cueing benefits. Cueing benefits were strongest for associations and participants with the poorest initial learning. These findings expand our knowledge of the conditions under which targeted memory reactivation can benefit memory, and in doing so, support the notion that reactivation during awake time periods improves memory stabilization