Theory and applications of artificial neural networks

In this thesis some fundamental theoretical problems about artificial neural networks and their application in communication and control systems are discussed. We consider the convergence properties of the Back-Propagation algorithm which is widely used for training of artificial neural networks, and two stepsize variation techniques are proposed to accelerate convergence. Simulation results demonstrate significant improvement over conventional Back-Propagation algorithms. We also discuss the relationship between generalization performance of artificial neural networks and their structure and representation strategy. It is shown that the structure of the network which represent a priori knowledge of the environment has a strong influence on generalization performance. A Theorem about the number of hidden units and the capacity of self-association MLP (Multi-Layer Perceptron) type network is also given in the thesis. In the application part of the thesis, we discuss the feasibility of using artificial neural networks for nonlinear system identification. Some advantages and disadvantages of this approach are analyzed. The thesis continues with a study of artificial neural networks applied to communication channel equalization and the problem of call access control in broadband ATM (Asynchronous Transfer Mode) communication networks. A final chapter provides overall conclusions and suggestions for further work

A study of the experiential service design process at a luxury hotel

This thesis explores the process of designing experiential services at a luxury hotel. These processes were surfaced by means of a methodology that used the principles of jazz improvisation. Due to similarities between experiential service design and elements in jazz improvisation, representing experiential service design through the jazz improvisation metaphor leads to a new framework for exploring the process of experiential service design that is iterative in nature. A gap in the service design literature is that experiential service design is not operationalized in organizational improvisation, and one contribution from this study will be to fill that gap. This study contributes to the field of knowledge by exposing a new perspective on how experiential services can be better designed by adapting some of the design tools from this luxury hotel; a second contribution is a recommendation for how the improvisational lens works as an investigative tool to research experiential organizations. In the process, some new dimensions to understanding complexity are contributed. The research process utilized qualitative research methods. Frank Barrett (1998) identified seven characteristics of jazz improvisation which I have used as a heuristic device: 1) provocative competence (i.e., deliberately creating disruption); 2) embracing errors as learning sources; 3) minimal structures that allow for maximum flexibility; 4) distributed task (i.e., an ongoing give and take); 5) reliance on retrospective sensemaking (organizational members as bricoleurs, making use of whatever is at hand); 6) hanging out (connecting through communities of practice); and 7) alternating between soloing and supporting. This research is grounded in the body of literature regarding complexity, organizational improvisation, service design and experience design. The role of heterogeneous minimal structures that are fluid and optimize uncertainty is central to this investigation. Themes such as sensemaking and the role of story, meaning-making, organizational actors' use of tangible and intangible design skills, and embracing ambiguity in efforts to design experiential services are explored throughout the dissertation. The anticipatory nature of experiential service design is a principle outcome from the data that is incorporated into the new conceptual framework highlighting a "posture of service"

Transmetteurs photoniques sur silicium pour les transmissions optiques à grande capacité

Les applications exigeant des très nombreuses données (médias sociaux, diffusion vidéo en continu, mégadonnées, etc.) se développent à un rythme rapide, ce qui nécessite de plus en plus de liaisons optiques ultra-rapides. Ceci implique le développment des transmetteurs optiques intégrés et à bas coût et plus particulirement en photonique sur silicium en raison de ses avantages par rapport aux autres technologies (LiNbO3 et InP), tel que la compatibilité avec le procédé de fabrication CMOS. Les modulateurs optoélectronique sont un élément essentiel dans la communication op-tique. Beaucoup de travaux de recherche sont consacrées au développement de dispositifs optiques haut débit efficaces. Cependant, la conception de modulateurs en photonique sur sili-cium (SiP) haut débit est diffcile, principalement en raison de l'absence d'effet électro-optique intrinsèque dans le silicium. De nouvelles approches et de architectures plus performances doivent être développées afin de satisfaire aux critères réliés au système d'une liaison optique aux paramètres de conception au niveau du dispositif integré. En outre, la co-conception de circuits integrés photoniques sur silicium et CMOS est cruciale pour atteindre tout le potentiel de la technologie de photonique sur silicium. Ainsi cette thèse aborde les défits susmentionnés. Dans notre première contribution, nous préesentons pour la première fois un émetteur phononique sur silicium PAM-4 sans utiliser un convertisseur numérique analog (DAC)qui comprend un modulateur Mach Zehnder à électrodes segmentées SiP (LES-MZM) implémenté dans un procédé photonique sur silicium générique avec jonction PN latérale et son conducteur CMOS intégré. Des débits allant jusqu'à 38 Gb/s/chnnel sont obtenus sans utili-ser un convertisseur numérique-analogique externe. Nous présentons également une nouvelle procédure de génération de délai dans le excitateur de MOS complémentaire. Un effet, un délai robuste aussi petit que 7 ps est généré entre les canaux de conduite. Dans notre deuxième contribution, nous présentons pour la première fois un nouveau fac-teur de mérite (FDM) pour les modulateurs SiP qui inclut non seulement la perte optique et l'efficacité (comme les FDMs précédents), mais aussi la bande passante électro-optique du modulateur SiP (BWEO). Ce nouveau FDM peut faire correspondre les paramètres de conception physique du modulateur SiP à ses critères de performance au niveau du système, facilitant à la fois la conception du dispositif optique et l'optimisation du système. Pour la première fois nous définissons et utilisons la pénalité de puissance du modulateur (MPP) induite par le modulateur SiP pour étudier la dégradation des performances au niveau du système induite par le modulateur SiP dans une communication à base de modulation d'amplitude d'impulsion optique. Nous avons développé l'équation pour MPP qui inclut les facteurs de limitation du modulateur (perte optique, taux d'extinction limité et limitation de la bande passante électro-optique). Enfin, dans notre troisième contribution, une nouvelle méthodologie de conception pour les modulateurs en SiP intégré à haute débit est présentée. La nouvelle approche est basée sur la minimisation de la MPP SiP en optimisant l'architecture du modulateur et le point de fonctionnement. Pour ce processus, une conception en longueur unitaire du modulateur Mach Zehnder (MZM) peut être optimisée en suivant les spécifications du procédé de fabrication et les règles de conception. Cependant, la longueur et la tension de biais du d'éphaseur doivent être optimisées ensemble (par exemple selon vitesse de transmission et format de modulation). Pour vérifier l'approche d'optimisation proposée expérimentale mont, a conçu un modulateur photonique sur silicium en phase / quadrature de phase (IQ) ciblant le format de modulation 16-QAM à 60 Gigabaud. Les résultats expérimentaux prouvent la fiabilité de la méthodologie proposée. D'ailleurs, nous avons augmenté la vitesse de transmission jusqu'à 70 Gigabaud pour tester la limite de débit au système. Une transmission de données dos à dos avec des débits binaires de plus de 233 Gigabit/s/channel est observée. Cette méthodologie de conception ouvre ainsi la voie à la conception de la prochaine génération d'émetteurs intégrés à double polarisation 400+ Gigabit/s/channel.Data-hungry applications (social media, video streaming, big data, etc.) are expanding at a fast pace, growing demand for ultra-fast optical links. This driving force reveals need for low-cost, integrated optical transmitters and pushes research in silicon photonics because of its advantages over other platforms (i.e. LiNbO3 and InP), such as compatibility with CMOS fabrication processes, the ability of on-chip polarization manipulation, and cost effciency. Electro-optic modulators are an essential component of optical communication links and immense research is dedicated to developing effcient high-bitrate devices. However, the design of high-capacity Silicon Photonics (SiP) transmitters is challenging, mainly due to lack of inherent electro-optic effect in silicon. New design methodologies and performance merits have to be developed in order to map the system-level criteria of an optical link to the design parameters in device-level. In addition, co-design of silicon photonics and CMOS integrated circuits is crucial to reveal the full potential of silicon photonics. This thesis addresses the aforementioned challenges. In our frst contribution, for the frst time we present a DAC-less PAM-4 silicon photonic transmitter that includes a SiP lumped-element segmented-electrode Mach Zehnder modula-tor (LES-MZM) implemented in a generic silicon photonic process with lateral p-n junction and its co-designed CMOS driver. Using post processing, bitrates up to 38 Gb/s/channel are achieved without using an external digital to analog converter. We also presents a novel delay generation procedure in the CMOS driver. A robust delay as small as 7 ps is generated between the driving channels. In our second contribution, for the frst time we present a new figure of merit (FOM) for SiP modulators that includes not only the optical loss and effciency (like the prior FOMs), but also the SiP modulator electro-optic bandwidth ( BWEO). This new FOM can map SiP modulator physical design parameters to its system-level performance criteria, facilitating both device design and system optimization. For the frst time we define and employ the modulator power penalty (MPP) induced by the SiP modulator to study the system level performance degradation induced by SiP modulator in an optical pulse amplitude modulation link. We develope a closed-form equation for MPP that includes the SiP modulator limiting factors (optical loss, limited extinction ratio and electro-optic bandwidth limitation). Finally in our third contribution, we present a novel design methodology for integrated high capacity SiP modulators. The new approach is based on minimizing the power penalty of a SiP modulator (MPP) by optimizing modulator design and bias point. For the given process, a unit-length design of Mach Zehnder modulator (MZM) can be optimized following the process specifications and design rules. However, the length and the bias voltage of the phase shifter must be optimized together in a system context (e.g., baud rate and modulation format). Moreover, to verify the proposed optimization approach in experiment, we design an in-phase/quadrature-phase (IQ) silicon photonic modulator targeting 16-QAM modulation format at 60 Gbaud. Experimental results proves the reliability of our proposed methodology. We further push the baud rate up to 70 Gbaud to examine the capacity boundary of the device. Back to back data transmission with bitrates more than 233 Gb/s/channel are captured. This design methodology paves the way for designing the next generation of integrated dual- polarization 400+ Gb/s/channel transmitters

A Phase Change Memory and DRAM Based Framework For Energy-Efficient and High-Speed In-Memory Stochastic Computing

Convolutional Neural Networks (CNNs) have proven to be highly effective in various fields related to Artificial Intelligence (AI) and Machine Learning (ML). However, the significant computational and memory requirements of CNNs make their processing highly compute and memory-intensive. In particular, the multiply-accumulate (MAC) operation, which is a fundamental building block of CNNs, requires enormous arithmetic operations. As the input dataset size increases, the traditional processor-centric von-Neumann computing architecture becomes ill-suited for CNN-based applications. This results in exponentially higher latency and energy costs, making the processing of CNNs highly challenging. To overcome these challenges, researchers have explored the Processing-In Memory (PIM) technique, which involves placing the processing unit inside or near the memory unit. This approach reduces data migration length and utilizes the internal memory bandwidth at the memory chip level. However, developing a reliable PIM-based system with minimal hardware modifications and design complexity remains a significant challenge. The proposed solution in the report suggests utilizing different memory technologies, such as Dynamic RAM (DRAM) and phase change memory (PCM), with Stochastic arithmetic and minimal add-on logic. Stochastic computing is a technique that uses random numbers to perform arithmetic operations instead of traditional binary representation. This technique reduces hardware requirements for CNN\u27s arithmetic operations, making it possible to implement them with minimal add-on logic. The report details the workflow for performing arithmetical operations used by CNNs, including MAC, activation, and floating-point functions. The proposed solution includes designs for scalable Stochastic Number Generator (SNG), DRAM CNN accelerator, non-volatile memory (NVM) class PCRAM-based CNN accelerator, and DRAM-based stochastic to binary conversion (StoB) for in-situ deep learning. These designs utilize stochastic computing to reduce the hardware requirements for CNN\u27s arithmetic operations and enable energy and time-efficient processing of CNNs. The report also identifies future research directions for the proposed designs, including in-situ PCRAM-based SNG, ODIN (A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-Situ Neural Network Processing in Phase Change RAM), ATRIA (Bit-Parallel Stochastic Arithmetic Based Accelerator for In-DRAM CNN Processing), and AGNI (In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning), and presents initial findings for these ideas. In summary, the proposed solution in the report offers a comprehensive approach to address the challenges of processing CNNs, and the proposed designs have the potential to improve the energy and time efficiency of CNNs significantly. Using Stochastic Computing and different memory technologies enables the development of reliable PIM-based systems with minimal hardware modifications and design complexity, providing a promising path for the future of CNN-based applications

Advanced Applications of Rapid Prototyping Technology in Modern Engineering

Rapid prototyping (RP) technology has been widely known and appreciated due to its flexible and customized manufacturing capabilities. The widely studied RP techniques include stereolithography apparatus (SLA), selective laser sintering (SLS), three-dimensional printing (3DP), fused deposition modeling (FDM), 3D plotting, solid ground curing (SGC), multiphase jet solidification (MJS), laminated object manufacturing (LOM). Different techniques are associated with different materials and/or processing principles and thus are devoted to specific applications. RP technology has no longer been only for prototype building rather has been extended for real industrial manufacturing solutions. Today, the RP technology has contributed to almost all engineering areas that include mechanical, materials, industrial, aerospace, electrical and most recently biomedical engineering. This book aims to present the advanced development of RP technologies in various engineering areas as the solutions to the real world engineering problems

Recent Advances in Wireless Communications and Networks

This book focuses on the current hottest issues from the lowest layers to the upper layers of wireless communication networks and provides "real-time" research progress on these issues. The authors have made every effort to systematically organize the information on these topics to make it easily accessible to readers of any level. This book also maintains the balance between current research results and their theoretical support. In this book, a variety of novel techniques in wireless communications and networks are investigated. The authors attempt to present these topics in detail. Insightful and reader-friendly descriptions are presented to nourish readers of any level, from practicing and knowledgeable communication engineers to beginning or professional researchers. All interested readers can easily find noteworthy materials in much greater detail than in previous publications and in the references cited in these chapters

Cross-Layer Pathfinding for Off-Chip Interconnects

Off-chip interconnects for integrated circuits (ICs) today induce a diverse design space, spanning many different applications that require transmission of data at various bandwidths, latencies and link lengths. Off-chip interconnect design solutions are also variously sensitive to system performance, power and cost metrics, while also having a strong impact on these metrics. The costs associated with off-chip interconnects include die area, package (PKG) and printed circuit board (PCB) area, technology and bill of materials (BOM). Choices made regarding off-chip interconnects are fundamental to product definition, architecture, design implementation and technology enablement. Given their cross-layer impact, it is imperative that a cross-layer approach be employed to architect and analyze off-chip interconnects up front, so that a top-down design flow can comprehend the cross-layer impacts and correctly assess the system performance, power and cost tradeoffs for off-chip interconnects. Chip architects are not exposed to all the tradeoffs at the physical and circuit implementation or technology layers, and often lack the tools to accurately assess off-chip interconnects. Furthermore, the collaterals needed for a detailed analysis are often lacking when the chip is architected; these include circuit design and layout, PKG and PCB layout, and physical floorplan and implementation. To address the need for a framework that enables architects to assess the system-level impact of off-chip interconnects, this thesis presents power-area-timing (PAT) models for off-chip interconnects, optimization and planning tools with the appropriate abstraction using these PAT models, and die/PKG/PCB co-design methods that help expose the off-chip interconnect cross-layer metrics to the die/PKG/PCB design flows. Together, these models, tools and methods enable cross-layer optimization that allows for a top-down definition and exploration of the design space and helps converge on the correct off-chip interconnect implementation and technology choice. The tools presented cover off-chip memory interfaces for mobile and server products, silicon photonic interfaces, 2.5D silicon interposers and 3D through-silicon vias (TSVs). The goal of the cross-layer framework is to assess the key metrics of the interconnect (such as timing, latency, active/idle/sleep power, and area/cost) at an appropriate level of abstraction by being able to do this across layers of the design flow. In additional to signal interconnect, this thesis also explores the need for such cross-layer pathfinding for power distribution networks (PDN), where the system-on-chip (SoC) floorplan and pinmap must be optimized before the collateral layouts for PDN analysis are ready. Altogether, the developed cross-layer pathfinding methodology for off-chip interconnects enables more rapid and thorough exploration of a vast design space of off-chip parallel and serial links, inter-die and inter-chiplet links and silicon photonics. Such exploration will pave the way for off-chip interconnect technology enablement that is optimized for system needs. The basis of the framework can be extended to cover other interconnect technology as well, since it fundamentally relates to system-level metrics that are common to all off-chip interconnects

NASA Tech Briefs, July 2013

Dielectrophoresis-Based Particle Sensor Using Nanoelectrode Arrays; Multi-Dimensional Damage Detection for Surfaces and Structures; ULTRA: Underwater Localization for Transit and Reconnaissance Autonomy; Autonomous Cryogenic Leak Detector for Improving Launch Site Operations; Submillimeter Planetary Atmospheric Chemistry Exploration Sounder; Method for Reduction of Silver Biocide Plating on Metal Surfaces; Silicon Micromachined Microlens Array for THz Antennas; Forward-Looking IED Detector Ground Penetrating Radar; Fully Printed, Flexible, Phased Array Antenna for Lunar Surface Communication, Battery Charge Equalizer with Transformer Array; An Efficient, Highly Flexible Multi-Channel Digital Downconverter Architecture; Dimmable Electronic Ballast for a Gas Discharge Lamp; Conductive Carbon Nanotube Inks for Use with Desktop Inkjet Printing Technology; Enhanced Schapery Theory Software Development for Modeling Failure of Fiber-Reinforced Laminates; High-Performance, Low-Temperature-Operating, Long-Lifetime Aerospace Lubricants; Carbon Nanotube Microarrays Grown on Nanoflake Substrates; Differential Muon Tomography to Continuously Monitor Changes in the Composition of Subsurface Fluids; Microgravity Drill and Anchor System; 20 Granular Media-Based Tunable Passive Vibration Suppressor; 21 Miga Aero Actuator and 2D Machined Mechanical Binary Latch; Micro-XRF for In Situ Geological Exploration of Other Planets; Hydrogen-Enhanced Lunar Oxygen Extraction and Storage Using Only Solar Power; Uplift of Ionospheric Oxygen Ions During Extreme Magnetic Storms; Miniaturized, High-Speed, Modulated X-Ray Source; Hollow-Fiber Spacesuit Water Membrane Evaporator 25 High-Power Single-Mode 2.65-micrometers InGaAsSb/AlInGaAsSb Diode Lasers; Optical Device for Converting a Laser Beam Into Two Co-aligned but Oppositely Directed Beams; A Hybrid Fiber/Solid-State Regenerative Amplifier with Tunable Pulse Widths for Satellite Laser Ranging; X-Ray Diffractive Optics; SynGenics Optimization System (SynOptSys); 29 CFD Script for Rapid TPS Damage Assessment; radEq Add-On Module for CFD Solver Loci-CHEM; Science Opportunity Analyzer (SOA) Version 8; 30 Autonomous Byte Stream Randomizer; Distributed Engine Control Empirical/Analytical Verification Tools; Dynamic Server-Based KML Code Generator Method for Level-of-Detail Traversal of Geospatial Data; Automated Planning of Science Products Based on Nadir Overflights and Alerts for Onboard and Ground Processing; Linked Autonomous Interplanetary Satellite Orbit Navigation; Risk-Constrained Dynamic Programming for Optimal Mars Entry, Descent, and Landing; Scheduling Operations for Massive Heterogeneous Clusters; Deepak Condenser Model (DeCoM); Flight Software Math Library; Recirculating 1-K-Pot for Pulse-Tube Cryostats; 35 Method for Processing Lunar Regolith Using Microwaves; Wells for In Situ Extraction of Volatiles from Regolith (WIEVR); and Estimating the Backup Reaction Wheel Orientation Using Reaction Wheel Spin Rates Flight Telemetry from a Spacecraft

Sensors and Technologies in Spain: State-of-the-Art

The aim of this special issue was to provide a comprehensive view on the state-of-the-art sensor technology in Spain. Different problems cause the appearance and development of new sensor technologies and vice versa, the emergence of new sensors facilitates the solution of existing real problems. [...