Baseband Processing for 5G and Beyond: Algorithms, VLSI Architectures, and Co-design

In recent years the number of connected devices and the demand for high data-rates have been significantly increased. This enormous growth is more pronounced by the introduction of the Internet of things (IoT) in which several devices are interconnected to exchange data for various applications like smart homes and smart cities. Moreover, new applications such as eHealth, autonomous vehicles, and connected ambulances set new demands on the reliability, latency, and data-rate of wireless communication systems, pushing forward technology developments. Massive multiple-input multiple-output (MIMO) is a technology, which is employed in the 5G standard, offering the benefits to fulfill these requirements. In massive MIMO systems, base station (BS) is equipped with a very large number of antennas, serving several users equipments (UEs) simultaneously in the same time and frequency resource. The high spatial multiplexing in massive MIMO systems, improves the data rate, energy and spectral efficiencies as well as the link reliability of wireless communication systems. The link reliability can be further improved by employing channel coding technique. Spatially coupled serially concatenated codes (SC-SCCs) are promising channel coding schemes, which can meet the high-reliability demands of wireless communication systems beyond 5G (B5G). Given the close-to-capacity error correction performance and the potential to implement a high-throughput decoder, this class of code can be a good candidate for wireless systems B5G. In order to achieve the above-mentioned advantages, sophisticated algorithms are required, which impose challenges on the baseband signal processing. In case of massive MIMO systems, the processing is much more computationally intensive and the size of required memory to store channel data is increased significantly compared to conventional MIMO systems, which are due to the large size of the channel state information (CSI) matrix. In addition to the high computational complexity, meeting latency requirements is also crucial. Similarly, the decoding-performance gain of SC-SCCs also do come at the expense of increased implementation complexity. Moreover, selecting the proper choice of design parameters, decoding algorithm, and architecture will be challenging, since spatial coupling provides new degrees of freedom in code design, and therefore the design space becomes huge. The focus of this thesis is to perform co-optimization in different design levels to address the aforementioned challenges/requirements. To this end, we employ system-level characteristics to develop efficient algorithms and architectures for the following functional blocks of digital baseband processing. First, we present a fast Fourier transform (FFT), an inverse FFT (IFFT), and corresponding reordering scheme, which can significantly reduce the latency of orthogonal frequency-division multiplexing (OFDM) demodulation and modulation as well as the size of reordering memory. The corresponding VLSI architectures along with the application specific integrated circuit (ASIC) implementation results in a 28 nm CMOS technology are introduced. In case of a 2048-point FFT/IFFT, the proposed design leads to 42% reduction in the latency and size of reordering memory. Second, we propose a low-complexity massive MIMO detection scheme. The key idea is to exploit channel sparsity to reduce the size of CSI matrix and eventually perform linear detection followed by a non-linear post-processing in angular domain using the compressed CSI matrix. The VLSI architecture for a massive MIMO with 128 BS antennas and 16 UEs along with the synthesis results in a 28 nm technology are presented. As a result, the proposed scheme reduces the complexity and required memory by 35%–73% compared to traditional detectors while it has better detection performance. Finally, we perform a comprehensive design space exploration for the SC-SCCs to investigate the effect of different design parameters on decoding performance, latency, complexity, and hardware cost. Then, we develop different decoding algorithms for the SC-SCCs and discuss the associated decoding performance and complexity. Also, several high-level VLSI architectures along with the corresponding synthesis results in a 12 nm process are presented, and various design tradeoffs are provided for these decoding schemes

VLSI Implementation of Reconfigurable FFT Processor Using Vedic Mathematics

Fast Fourier transform has been used in wide range of applications such as digital signal processing and wireless communications. In this we present a implementation of reconfigurable FFT processor using single path delay feedback architecture. To eliminate the use of read only memory’s (ROM’S). These are used to store the twiddle factors. To achieve the ROM-less FFT processor the proposed architecture applies the bit parallel multipliers and reconfigurable complex multipliers, thus consuming less power. The proposed architecture, Reconfigurable FFT processor based on Vedic mathematics is designed, simulated and implemented using VIRTEX-5 FPGA. Urdhva Triyakbhyam algorithm is an ancient Vedic mathematic sutra, which is used to achieve the high performance. This reconfigurable DIF-FFT is having the high speed and small area as compared with other conventional DIF-FF

MDC FFT/IFFT Processor with 64-Point using Radix-4 Algorithm for MIMO-OFDM System

Abstract: Human needs with technical de vices are increasing rapidly. In order to meet their requirements the system should be accurate and fast. The fastness and accuracy of a system depends on its intra and inter peripherals/algorithms. In the view of t his, the proposed paper came into existence. MDC, we propose simple memory scheduling methods for input data and output bit/set-reversing, which again results in a full utilization rate in memory usage. It focuses on the development of the Fast Fourier Transform (FFT) algorithm, based on Decimation-In-Time (DIT) domain, calle d Radix-4 DIT-FFT algorithm. Verilog is used as a design entity and for simulation Xilinx ISE and modelsim. The synthesis results show that the computation for calculating the 64-point FFT is efficient in terms of speed and area is implemented on UMC 90-nm CMOS technology. This processor can be used in IEEE 802.16 WiMAX and 3G PP long term evolution applications

Design And Implementation Of Radix-4 Fast Fourier Transform In Asia Chip With 0.18 M Standard CMOS Technology [TK5102.9. S624 2008 f rb].

Jelmaan Fourier pantas (FFT) merupakan blok yang penting dan digunakan secara meluas dalam algoritma pemprosesan isyarat digital. The Fast Fourier Transform (FFT) is a critical block and widely used in digital signal processing algorithm

Improving Energy Efficiency of OFDM Using Adaptive Precision Reconfigurable FFT

International audienceBeing an essential issue in digital systems, especially battery-powered devices, energy efficiency has been the subject of intensive research. In this research, a multi-precision FFT module with dynamic run-time reconfigurability is proposed to trade off accuracy with the energy efficiency of OFDM in an SDR-based architecture. To support variable-size FFT, a reconfigurable memory-based architecture is investigated. It is revealed that the radix-4 FFT has the minimum computational complexity in this architecture. Regarding implementation constraints such as fixed-width memory, a noise model is exploited to statistically analyze the proposed architecture. The required FFT word-lengths for different criteria—namely BER, modulation scheme, FFT size, and SNR—are computed analytically and confirmed by simulations in AWGN and Rayleigh fading channels. At run-time, the most energy-efficient word-length is chosen and the FFT is reconfigured until the required application-specific BER is met. Evaluations show that the implementation area and the number of memory accesses are reduced. The results obtained from synthesizing basic operators of the proposed design on an FPGA show energy consumption experienced a saving of over 80 %

PERANCANGAN DAN IMPLEMENTASI ALGORTIMA FFT 64 TITIK MENGGUNAKAN MULTIPATH DELAY COMMUTATOR PADA FPGA

Dalam pengaplikasian Algoritma FFT, kecepatan komputasi, sederhana dalam implementasi dan hemat memori adalah hal yang harus diperhatikan. Untuk kebutuhan tersebut teknik yang paling cocok untuk implementasi adalah pipeline architecture. Keunggulan dari pipeline architecture adalah data bisa diparalelkan saat pemrosesan, bekerja secara real time, pengolahan secara kontinu dan mempunyai latency yang kecil. Pada penelitian ini dilakukan perancangan FFT dengan menggunakan salah satu varian dari teknik pipeline architecture yaitu MDC dikarenakan kontrol yang lebih simpel, jumlah data yang diproses adalah 64 subcarrier dengan menggunakan radix 2 peruraian dalam frekuensi untuk pendekatan algoritma FFT. Perancangan dilakukan berdasarkan standar yang sudah ditentukan. Selanjutnya hasil rancangan disimulasikan pada software ModelSim. Dari hasil pemodelan dan simulasi, kemudian di implementasikan ke perangkat FPGA. Hasil Implementasi menunjukkan bahwa perancangan prototype Algoritma FFT menggunakan teknik MDC dapat diimplementasikan pada board ATLYS Spartan-6. Hasil implementasi menunjukkan penggunaan resource slice registers sebesar 3,6%, penggunaan bonded IOBs sebesar 10,55%, dan delay process menghasilkan 22.900 ns, sedangkan pada penelitian sebelumnya dalam penggunaan resource slice registers sebesar 4,4%, penggunaan bonded IOBs sebesar 34,4% dan menghasilkan delay process 35.400 ns. Sehingga MDC merupakan solusi implementasi algoritma FFT dalam effisiensi memori dan kecepatan komputasi. Prototype ini menghasilkan sistem dengan periode minimum 15,895 ns dan frekuensi kerja 62,914 MHz