Ultra-Low Power Wake Up Receiver For Medical Implant Communications Service Transceiver

This thesis explores the specific requirements and challenges for the design of a dedicated wake-up receiver for medical implant communication services equipped with a novel “uncertain-IF†architecture combined with a high – Q filtering MEMS resonator and a free running CMOS ring oscillator as the RF LO. The receiver prototype, implements an IBM 0.18μm mixed-signal 7ML RF CMOS technology and achieves a sensitivity of -62 dBm at 404MHz while consuming \u3c100 μW from a 1 V supply

Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices

Low-cost test and tuning methods for difficult-to-measure specifications are presented in this research from the following perspectives: 1)"Safe" test and self-tuning for power converters: To avoid the risk of device under test (DUT) damage during conventional load/line regulation measurement on power converter, a "safe" alternate test structure is developed where the power converter (boost/buck converter) is placed in a different mode of operation during alternative test (light switching load) as opposed to standard test (heavy switching load) to prevent damage to the DUT during manufacturing test. Based on the alternative test structure, self-tuning methods for both boost and buck converters are also developed in this thesis. In addition, to make these test structures suitable for on-chip built-in self-test (BIST) application, a special sensing circuit has been designed and implemented. Stability analysis filters and appropriate models are also implemented to predict the DUT’s electrical stability condition during test and to further predict the values of tuning knobs needed for the tuning process. 2) High bandwidth RF signal generation: Up-convertion has been widely used in high frequency RF signal generation but mixer nonlinearity results in signal distortion that is difficult to eliminate with such methods. To address this problem, a framework for low-cost high-fidelity wideband RF signal generation is developed in this thesis. Depending on the band-limited target waveform, the input data for two interleaved DACs (digital-to-analog converters) system is optimized by a matrix-model-based algorithm in such a way that it minimizes the distortion between one of its image replicas in the frequency domain and the target RF waveform within a specified signal bandwidth. The approach is used to demonstrate how interferers with specified frequency characteristics can be synthesized at low cost for interference testing of RF communications systems. The frameworks presented in this thesis have a significant impact in enabling low-cost test and tuning of difficult-to-measure device specifications for power converter and high-speed devices.Ph.D

Ultra Low Power IEEE 802.15.4/ZIGBEE Compliant Transceiver

Low power wireless communications is the most demanding request among all wireless users. A battery life that can survive for years without being replaced, makes it realistic to implement many applications where the battery is unreachable (e.g. concrete walls) or expensive to change (e.g underground applications). IEEE 802.15.4/ZIGBEE standard is published to cover low power low cost applications, where the battery life can last for years, because of the 1% duty cycle of operation. A fully integrated 2.4GHz IEEE802.15.4 Compliant transceiver suitable for low power, low cost ZIGBEE applications is implemented. Direct conversion architecture is used in both Receiver and Transmitter, to achieve the minimum possible power and area. The chip is fabricated in a standard 0.18um CMOS technology. In the transmit mode, the transmitter chain (Modulator to PA) consumes 25mW, while in the receive mode, the iv receiver chain (LNA to Demodulator) consumes 5mW. The Integer-N Frequency Synthesizer consumes 8.5mW. Other Low power circuits are reported; A 13.56 Passive RFID tag and a low power ADC suitable for Built-In-Testing applications

Wireless Sensors for Health Monitoring of Marine Structures and Machinery

Remote structural and machinery health monitoring (SMHM) of marine structures such as ships, oil and gas rigs, freight container terminals, and marine energy platforms can ensure their reliability. However, the wired sensors currently used in these applications are difficult and expensive to install and maintain. Wireless Sensor Networks (WSN) can potentially replace them but there are significant capability gaps that currently prevent their long-term deployment in the harsh marine environment and the structurally-complex, compartmentalised, all-metal scenarios with high volume occupancy of piping, ducting and operational machinery represented by marine structures. These gaps are in sensing, processing and communication hardware and firmware capabilities, reduction of power consumption, hardware assembly and packaging for reliability in the marine environment, reliability of wireless connectivity in the complex metal structures, and software for WSN deployment planning in the marine environment. Taken together, these gaps highlight the need for a systems integration methodology for marine SMHM and this is the focus of the research presented in this thesis. The research takes an applied approach by first designing the hardware and firmware for two wireless sensing modules specifically for marine SMHM, one a novel eddy-current-based 3D module for measuring multi-axis metal structural displacement, the second a fully integrated module for monitoring of structure and machinery reliability. The research then addresses module assembly and packaging methods to ensure reliability in the marine environment, the development of an efficient methodology for characterising the reliability of wireless connectivity in complex metal structures, and development of user interface software for planning WSN deployment and for managing the collection of WSN data. These are then individually and collectively characterised and tested for performance and reliability in laboratory, land-based and marine deployments. In addition to the research outcomes in each of these individual aspects, the overall research outcome represents a systems integration methodology that now allows deployment, with a high expectation of reliability of marine SMHM WSNs

Robust sigma delta converters : and their application in low-power highly-digitized flexible receivers

In wireless communication industry, the convergence of stand-alone, single application transceiver IC’s into scalable, programmable and platform based transceiver ICs, has led to the possibility to create sophisticated mobile devices within a limited volume. These multi-standard (multi-mode), MIMO, SDR and cognitive radios, ask for more adaptability and flexibility on every abstraction level of the transceiver. The adaptability and flexibility of the receive paths require a digitized receiver architecture in which most of the adaptability and flexibility is shifted in the digital domain. This trend to ask for more adaptability and flexibility, but also more performance, higher efficiency and an increasing functionality per volume, has a major impact on the IP blocks such systems are built with. At the same time the increasing requirement for more digital processing in the same volume and for the same power has led to mainstream CMOS feature size scaling, leading to smaller, faster and more efficient transistors, optimized to increase processing efficiency per volume (smaller area, lower power consumption, faster digital processing). As wireless receivers is a comparably small market compared to digital processors, the receivers also have to be designed in a digitally optimized technology, as the processor and transceiver are on the same chip to reduce device volume. This asks for a generalized approach, which maps application requirements of complex systems (such as wireless receivers) on the advantages these digitally optimized technologies bring. First, the application trends are gathered in five quality indicators being: (algorithmic) accuracy, robustness, flexibility, efficiency, and emission, of which the last one is not further analyzed in this thesis. Secondly, using the quality indicators, it is identified that by introducing (or increasing) digitization at every abstraction level of a system, the advantages of modern digitally optimized technologies can be exploited. For a system on a chip, these abstraction levels are: system/application level, analog IP architecture level, circuit topology level and layout level. In this thesis, the quality indicators together with the digitization at different abstraction levels are applied to S¿ modulators. S¿ modulator performance properties are categorized into the proposed quality indicators. Next, it is identified what determines the accuracy, robustness, flexibility and efficiency of a S¿ modulator. Important modulator performance parameters, design parameter relations, and performance-cost relations are derived. Finally, several implementations are presented, which are designed using the found relations. At least one implementation example is shown for each level of digitization. At system level, a flexible (N)ZIF receiver architecture is digitized by shifting the ADC closer to the antenna, reducing the amount of analog signal conditioning required in front of the ADC, and shifting the re-configurability of such a receiver into the digital domain as much as possible. Being closer to the antenna, and because of the increased receiver flexibility, a high performance, multi-mode ADC is required. In this thesis, it is proven that such multi-mode ADCs can be made at low area and power consumption. At analog IP architecture level, a smarter S¿ modulator architecture is found, which combines the advantages of 1-bit and multi-bit modulators. The analog loop filter is partly digitized, and analog circuit blocks are replaced by a digital filter, leading to an area and power efficient design, which above all is very portable, and has the potential to become a good candidate for the ADC in multimode receivers. At circuit and layout level, analog circuits are designed in the same way as digital circuits are. Analog IP blocks are split up in analog unit cells, which are put in a library. For each analog unit cell, a p-cell layout view is created. Once such a library is available, different IP blocks can be created using the same unit cells and using the automatic routing tools normally used for digital circuits. The library of unit cells can be ported to a next technology very quickly, as the unit cells are very simple circuits, increasing portability of IP blocks made with these unit cells. In this thesis, several modulators are presented that are designed using this digital design methodology. A high clock frequency in the giga-hertz range is used to test technology speed. The presented modulators have a small area and low power consumption. A modulator is ported from a 65nm to a 45nm technology in one month without making changes to the unit cells, or IP architecture, proving that this design methodology leads to very portable designs. The generalized system property categorization in quality indicators, and the digitization at different levels of system design, is named the digital design methodology. In this thesis this methodology is successfully applied to S¿ modulators, leading to high quality, mixed-signal S¿ modulator IP, which is more accurate, more robust, more flexible and/or more efficient

Robust sigma delta converters : and their application in low-power highly-digitized flexible receivers

In wireless communication industry, the convergence of stand-alone, single application transceiver IC’s into scalable, programmable and platform based transceiver ICs, has led to the possibility to create sophisticated mobile devices within a limited volume. These multi-standard (multi-mode), MIMO, SDR and cognitive radios, ask for more adaptability and flexibility on every abstraction level of the transceiver. The adaptability and flexibility of the receive paths require a digitized receiver architecture in which most of the adaptability and flexibility is shifted in the digital domain. This trend to ask for more adaptability and flexibility, but also more performance, higher efficiency and an increasing functionality per volume, has a major impact on the IP blocks such systems are built with. At the same time the increasing requirement for more digital processing in the same volume and for the same power has led to mainstream CMOS feature size scaling, leading to smaller, faster and more efficient transistors, optimized to increase processing efficiency per volume (smaller area, lower power consumption, faster digital processing). As wireless receivers is a comparably small market compared to digital processors, the receivers also have to be designed in a digitally optimized technology, as the processor and transceiver are on the same chip to reduce device volume. This asks for a generalized approach, which maps application requirements of complex systems (such as wireless receivers) on the advantages these digitally optimized technologies bring. First, the application trends are gathered in five quality indicators being: (algorithmic) accuracy, robustness, flexibility, efficiency, and emission, of which the last one is not further analyzed in this thesis. Secondly, using the quality indicators, it is identified that by introducing (or increasing) digitization at every abstraction level of a system, the advantages of modern digitally optimized technologies can be exploited. For a system on a chip, these abstraction levels are: system/application level, analog IP architecture level, circuit topology level and layout level. In this thesis, the quality indicators together with the digitization at different abstraction levels are applied to S¿ modulators. S¿ modulator performance properties are categorized into the proposed quality indicators. Next, it is identified what determines the accuracy, robustness, flexibility and efficiency of a S¿ modulator. Important modulator performance parameters, design parameter relations, and performance-cost relations are derived. Finally, several implementations are presented, which are designed using the found relations. At least one implementation example is shown for each level of digitization. At system level, a flexible (N)ZIF receiver architecture is digitized by shifting the ADC closer to the antenna, reducing the amount of analog signal conditioning required in front of the ADC, and shifting the re-configurability of such a receiver into the digital domain as much as possible. Being closer to the antenna, and because of the increased receiver flexibility, a high performance, multi-mode ADC is required. In this thesis, it is proven that such multi-mode ADCs can be made at low area and power consumption. At analog IP architecture level, a smarter S¿ modulator architecture is found, which combines the advantages of 1-bit and multi-bit modulators. The analog loop filter is partly digitized, and analog circuit blocks are replaced by a digital filter, leading to an area and power efficient design, which above all is very portable, and has the potential to become a good candidate for the ADC in multimode receivers. At circuit and layout level, analog circuits are designed in the same way as digital circuits are. Analog IP blocks are split up in analog unit cells, which are put in a library. For each analog unit cell, a p-cell layout view is created. Once such a library is available, different IP blocks can be created using the same unit cells and using the automatic routing tools normally used for digital circuits. The library of unit cells can be ported to a next technology very quickly, as the unit cells are very simple circuits, increasing portability of IP blocks made with these unit cells. In this thesis, several modulators are presented that are designed using this digital design methodology. A high clock frequency in the giga-hertz range is used to test technology speed. The presented modulators have a small area and low power consumption. A modulator is ported from a 65nm to a 45nm technology in one month without making changes to the unit cells, or IP architecture, proving that this design methodology leads to very portable designs. The generalized system property categorization in quality indicators, and the digitization at different levels of system design, is named the digital design methodology. In this thesis this methodology is successfully applied to S¿ modulators, leading to high quality, mixed-signal S¿ modulator IP, which is more accurate, more robust, more flexible and/or more efficient

Proceedings of the Fifth International Mobile Satellite Conference 1997

Satellite-based mobile communications systems provide voice and data communications to users over a vast geographic area. The users may communicate via mobile or hand-held terminals, which may also provide access to terrestrial communications services. While previous International Mobile Satellite Conferences have concentrated on technical advances and the increasing worldwide commercial activities, this conference focuses on the next generation of mobile satellite services. The approximately 80 papers included here cover sessions in the following areas: networking and protocols; code division multiple access technologies; demand, economics and technology issues; current and planned systems; propagation; terminal technology; modulation and coding advances; spacecraft technology; advanced systems; and applications and experiments