A High-Efficiency RF Harvester with Maximum Power Point Tracking

This paper presents the implementation of a high-efficiency radiofrequency (RF) harvester, which consists of a rectenna and a maximum power point tracker (MPPT). The rectenna was characterized from -30 dBm to -10 dBm at 808 MHz, achieving an efficiency higher than 60% at -10 dBm. Experimental results also show that the rectenna can be well modelled as a Thévenin equivalent circuit, which allows the use of a simple ensuing MPPT. The complete RF harvester was tested, achieving an overall efficiency near 50% at -10 dBm. Further tests were performed powering a sensor node from a nearby antenna.Peer ReviewedPostprint (published version

Dickson Charge Pump Rectifier using Ultra-Low Power (ULP) Diode for BAN Applications

High power consumption and small battery size severely limit the operating time of devices in Body Area Network (BAN). Radio Frequency (RF) harvesting system can be one of the ways to solve this constraint. Rectifier converts ambient RF into direct current (DC). In a conventional rectifier circuit, Schottky diodes have been considered as an attractive candidate due to their low forward voltage drop and fast switching speed. However, Schottky diodes are not properly modelled in Complementary Metal Oxide Semiconductor (CMOS) technologies which restrict their usefulness in low -cost applications, where high integration levels are desired. Thus, an efficient model of Schottky diode in an integrated circuit (IC) domain is needed. For this reason, Ultra-Low Power (ULP) diode has been proposed in the IC rectifier designs. The performance of ULP diode was compared with diode-connected MOSFET based on Dickson topology and Villard voltage multiplier in 130nm Silterra process technology. The correlation of the design parameters to the performance of voltage rectifier was analysed. The results show that the efficiency of the voltage multiplier has successfully increased more than double based on the optimisation of the design parameters

Analysis of the optimum gain of a high-pass l-matching network for rectennas

Rectennas, which mainly consist of an antenna, matching network, and rectifier, are used to harvest radiofrequency energy in order to power tiny sensor nodes, e.g., the nodes of the Internet of Things. This paper demonstrates for the first time, the existence of an optimum voltage gain for high-pass L-matching networks used in rectennas by deriving an analytical expression. The optimum gain is that which leads to maximum power efficiency of the rectenna. Here, apart from the L-matching network, a Schottky single-diode rectifier was used for the rectenna, which was optimized at 868 MHz for a power range from -30 dBm to -10 dBm. As the theoretical expression depends on parameters not very well-known a priori, an accurate search of the optimum gain for each power level was performed via simulations. Experimental results show remarkable power efficiencies ranging from 16% at -30 dBm to 55% at -10 dBm, which are for almost all the tested power levels the highest published in the literature for similar designs.Postprint (author's final draft

An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications

Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μ m CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 m m 2 . The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μ W. The analog part of the design consumes only 36 μ W, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches

Inductively Coupled CMOS Power Receiver For Embedded Microsensors

Inductively coupled power transfer can extend the lifetime of embedded microsensors that save costs, energy, and lives. To expand the microsensors' functionality, the transferred power needs to be maximized. Plus, the power receiver needs to handle wide coupling variations in real applications. Therefore, the objective of this research is to design a power receiver that outputs the highest power for the widest coupling range. This research proposes a switched resonant half-bridge power stage that adjusts both energy transfer frequency and duration so the output power is maximally high. A maximum power point (MPP) theory is also developed to predict the optimal settings of the power stage with 98.6% accuracy. Finally, this research addresses the system integration challenges such as synchronization and over-voltage protection. The fabricated self-synchronized prototype outputs up to 89% of the available power across 0.067%~7.9% coupling range. The output power (in percentage of available power) and coupling range are 1.3× and 13× higher than the comparable state of the arts.Ph.D

Analysis and design of a subthreshold CMOS Schmitt trigger circuit

Tese (doutorado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Engenharia Elétrica, Florianópolis, 2017.Nesta tese, o disparador Schmitt (ou Schmitt trigger) CMOS clássico (ST) operando em inversão fraca é analisado. A transferência de tensão DC completa é determinada, incluindo expressões analíticas para as tensões dos nós internos. A transferência de tensão DC resultante do ST apresenta um comportamento contínuo mesmo na presença da histerese. Nesse caso, a característica da tensão de saída entre os limites da histerese é formada por um segmento metaestável, que pode ser explicado em termos das resistências negativas dos subcircuitos NMOS e PMOS do ST. A tensão mínima para o aparecimento da histerese é determinada fazendo-se a análise de pequenos sinais. A análise de pequenos sinais também é utilizada para a estimativa da largura do laço de histerese. É mostrado que a histerese não aparece para tensões de alimentação menores que 75 mV em 300 K. A análise do ST operando como amplificador também foi feita. A razão ótima dos transistores foi determinada com o objetivo de se maximizar o ganho de tensão. A comparação do disparador Schmitt com o inversor CMOS convencional destaca as vantagens e desvantagens de cada um para aplicações de ultra-baixa tensão. Também é mostrado que o ST é teoricamente capaz de operar (com ganho de tensão absoluto ?1) com uma tensão de alimentação tão baixa quanto 31.5 mV, a qual é menor do que o conhecido limite prévio de 36 mV, para o inversor convencional. Como amplificador, o ST possui ganho de tensão absoluto consideravelmente maior que o inversor convencional na mesma tensão de alimentação. Três circuitos integrados foram projetados e fabricados para estudar o comportamento do ST com tensões de alimentação entre 50 mV e 1000 mV.Abstract : In this thesis, the classical CMOS Schmitt trigger (ST) operating in weak inversion is analyzed. The complete DC voltage transfer characteristic is determined, including analytical expressions for the internal node voltage. The resulting voltage transfer characteristic of the ST presents a continuous output behavior even when hysteresis is present. In this case, the output voltage characteristic between the hysteresis limits is formed by a metastable segment, which can be explained in terms of the negative resistance of the NMOS and PMOS subcircuits of the ST. The minimum supply voltage at which hysteresis appears is determined carrying out small-signal analysis, which is also used to estimate the hysteresis width. It is shown that hysteresis does not appear for supply voltages lower than 75 mV at 300 K. The analysis of the ST operating as a voltage amplifier was also carried out. Optimum transistor ratios were determined aiming at voltage gain maximization. The comparison of the ST with the standard CMOS inverter highlights the relative benefits and drawbacks of each one in ULV applications. It is also shown that the ST is theoretically capable of operating (voltage gain ?1) at a supply voltage as low as 31.5 mV, which is lower than the well-known limit of 36 mV, for the standard CMOS inverter. As an amplifier, the ST shows considerable higher absolute voltage gains than those showed by the conventional inverter at the same supply voltages. Three test chips were designed and fabricated to study the operation of the ST at supply voltages between 50 mV and 1000 mV

Integrated Data and Energy Communication Network: A Comprehensive Survey

OAPA In order to satisfy the power thirsty of communication devices in the imminent 5G era, wireless charging techniques have attracted much attention both from the academic and industrial communities. Although the inductive coupling and magnetic resonance based charging techniques are indeed capable of supplying energy in a wireless manner, they tend to restrict the freedom of movement. By contrast, RF signals are capable of supplying energy over distances, which are gradually inclining closer to our ultimate goal – charging anytime and anywhere. Furthermore, transmitters capable of emitting RF signals have been widely deployed, such as TV towers, cellular base stations and Wi-Fi access points. This communication infrastructure may indeed be employed also for wireless energy transfer (WET). Therefore, no extra investment in dedicated WET infrastructure is required. However, allowing RF signal based WET may impair the wireless information transfer (WIT) operating in the same spectrum. Hence, it is crucial to coordinate and balance WET and WIT for simultaneous wireless information and power transfer (SWIPT), which evolves to Integrated Data and Energy communication Networks (IDENs). To this end, a ubiquitous IDEN architecture is introduced by summarising its natural heterogeneity and by synthesising a diverse range of integrated WET and WIT scenarios. Then the inherent relationship between WET and WIT is revealed from an information theoretical perspective, which is followed by the critical appraisal of the hardware enabling techniques extracting energy from RF signals. Furthermore, the transceiver design, resource allocation and user scheduling as well as networking aspects are elaborated on. In a nutshell, this treatise can be used as a handbook for researchers and engineers, who are interested in enriching their knowledge base of IDENs and in putting this vision into practice