29,054 research outputs found
High-level synthesis under I/O Timing and Memory constraints
The design of complex Systems-on-Chips implies to take into account
communication and memory access constraints for the integration of dedicated
hardware accelerator. In this paper, we present a methodology and a tool that
allow the High-Level Synthesis of DSP algorithm, under both I/O timing and
memory constraints. Based on formal models and a generic architecture, this
tool helps the designer to find a reasonable trade-off between both the
required I/O timing behavior and the internal memory access parallelism of the
circuit. The interest of our approach is demonstrated on the case study of a
FFT algorithm
Constraint Centric Scheduling Guide
The advent of architectures with software-exposed resources (Spatial Architectures) has created a demand for universally applicable scheduling techniques. This paper describes our generalized spatial scheduling framework, formulated with Integer Linear Programming, and specifically accomplishes two goals. First, using the ?Simple? architecture, it illustrates how to use our open-source tool to create a customized scheduler and covers problem formulation with ILP and GAMS. Second, it summarizes results on the application to three real architectures (TRIPS,DySER,PLUG), demonstrating the technique?s practicality and competitiveness with existing schedulers
Schedulability analysis of timed CSP models using the PAT model checker
Timed CSP can be used to model and analyse real-time and concurrent behaviour of embedded control systems. Practical CSP implementations combine the CSP model of a real-time control system with prioritized scheduling to achieve efficient and orderly use of limited resources. Schedulability analysis of a timed CSP model of a system with respect to a scheduling scheme and a particular execution platform is important to ensure that the system design satisfies its timing requirements. In this paper, we propose a framework to analyse schedulability of CSP-based designs for non-preemptive fixed-priority multiprocessor scheduling. The framework is based on the PAT model checker and the analysis is done with dense-time model checking on timed CSP models. We also provide a schedulability analysis workflow to construct and analyse, using the proposed framework, a timed CSP model with scheduling from an initial untimed CSP model without scheduling. We demonstrate our schedulability analysis workflow on a case study of control software design for a mobile robot. The proposed approach provides non-pessimistic schedulability results
Simulation of Mixed Critical In-vehicular Networks
Future automotive applications ranging from advanced driver assistance to
autonomous driving will largely increase demands on in-vehicular networks. Data
flows of high bandwidth or low latency requirements, but in particular many
additional communication relations will introduce a new level of complexity to
the in-car communication system. It is expected that future communication
backbones which interconnect sensors and actuators with ECU in cars will be
built on Ethernet technologies. However, signalling from different application
domains demands for network services of tailored attributes, including
real-time transmission protocols as defined in the TSN Ethernet extensions.
These QoS constraints will increase network complexity even further.
Event-based simulation is a key technology to master the challenges of an
in-car network design. This chapter introduces the domain-specific aspects and
simulation models for in-vehicular networks and presents an overview of the
car-centric network design process. Starting from a domain specific description
language, we cover the corresponding simulation models with their workflows and
apply our approach to a related case study for an in-car network of a premium
car
Recommended from our members
Chippe : a system for constraint driven behavioral synthesis
This report describes the Chippe system, gives some background previous work and describes several sample design runs of the system. Also presented are the sources of the design tradeoffs used by Chippe, and overview of the internal design model, and experiences using the system
- …