Novel solution for compiler infrastructure for embedded processors

Ова докторска теза описује и анализира приступ развоју Це компајлера за наменске процесоре. Такав компајлер захтева имплементацију посебних техника и алгоритама, претежно специфичних за нерегуларне процесорске архитектуре, да би генерисао ефикасан код, и при том је потребно да испуњава индустријске стандарде по питању робустности, разумљивости кода, могућности одржавања и проширивости. У ту сврху је предложена нова компајлерска инфраструктура над којом је имплементиран компајлер за Cirrus Coyote 32 ДСП. Квалитет генерисаног кода поређен је са квалитетом кода генерисног од стране већ постојећег компајлера за тај процесор. Уједно, одређени елементи организације компајлера су упоређени са популарним компајлерима отвореног кода GCC и LLVM.Ova doktorska teza opisuje i analizira pristup razvoju Ce kompajlera za namenske procesore. Takav kompajler zahteva implementaciju posebnih tehnika i algoritama, pretežno specifičnih za neregularne procesorske arhitekture, da bi generisao efikasan kod, i pri tom je potrebno da ispunjava industrijske standarde po pitanju robustnosti, razumljivosti koda, mogućnosti održavanja i proširivosti. U tu svrhu je predložena nova kompajlerska infrastruktura nad kojom je implementiran kompajler za Cirrus Coyote 32 DSP. Kvalitet generisanog koda poređen je sa kvalitetom koda generisnog od strane već postojećeg kompajlera za taj procesor. Ujedno, određeni elementi organizacije kompajlera su upoređeni sa popularnim kompajlerima otvorenog koda GCC i LLVM.This PhD thesis describes and analyses an approach to development of C language compiler for embedded processors. That kind of compiler requires implementation of special techniques and algorithms, mostly specific for irregular processor architectures, in order to be able to generate efficient code, whereas still meeting industrial strength standard by beeing robust, understandable, maintainable, and extensible. For this purpose the new compiler insfrastructure is proposed and on top of it a compiler for Cirrus Logic Coyote 32 DSP is built. Quality of the code generated by that compiler is compared with code generated by the previous compiler for the same processor architecture. Some elements of the compiler design are also compared to popular open source compilers GCC and LLVM

Characterizing function inlining with genetic programming

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (leaves 74-75).Function inlining is a compiler optimization where the function call is replaced by the code from the function itself. Using a form of machine learning called genetic programming, this thesis examines which factors are important in determining which function calls to inline to maximize performance. A number of different heuristics are generated for inlining decisions in the Trimaran compiler, which improve on performance from the current default inlining heuristic. Also, trends in function inlining are examined over the thousands of compilation runs that are completed.by Chris Yu.M.Eng

Fast Fourier transforms on energy-efficient application-specific processors

Many of the current applications used in battery powered devices are from digital signal processing, telecommunication, and multimedia domains. Traditionally application-specific fixed-function circuits have been used in these designs in form of application-specific integrated circuits (ASIC) to reach the required performance and energy-efficiency. The complexity of these applications has increased over the years, thus the design complexity has increased even faster, which implies increased design time. At the same time, there are more and more standards to be supported, thus using optimised fixed-function implementations for all the functions in all the standards is impractical. The non-recurring engineering costs for integrated circuits have also increased significantly, so manufacturers can only afford fewer chip iterations. Although tailoring the circuit for a specific application provides the best performance and/or energy-efficiency, such approach lacks flexibility. E.g., if an error is found after the manufacturing, an expensive chip iteration is required. In addition, new functionalities cannot be added afterwards to support evolution of standards. Flexibility can be obtained with software based implementation technologies. Unfortunately, general-purpose processors do not provide the energy-efficiency of the fixed-function circuit designs. A useful trade-off between flexibility and performance is implementation based on application-specific processors (ASP) where programmability provides the flexibility and computational resources customised for the given application provide the performance. In this Thesis, application-specific processors are considered by using fast Fourier transform as the representative algorithm. The architectural template used here is transport triggered architecture (TTA) which resembles very long instruction word machines but the operand execution resembles data flow machines rather than traditional operand triggering. The developed TTA processors exploit inherent parallelism of the application. In addition, several characteristics of the application have been identified and those are exploited by developing customised functional units for speeding up the execution. Several customisations are proposed for the data path of the processor but it is also important to match the memory bandwidth to the computation speed. This calls for a memory organisation supporting parallel memory accesses. The proposed optimisations have been used to improve the energy-efficiency of the processor and experiments show that a programmable solution can have energy-efficiency comparable to fixed-function ASIC designs