Through-Life Monitoring of the impact of vibration on the reliability of area array packages using Non- Destructive Testing

In order to keep up with the demands for faster, cheaper and smaller electronics, the packaging industry has evolved tremendously. Area array packages like flip chips and ball grid arrays are therefore widely used in modern day electronics. However, from the reliability standpoint, solder joints in these area array packages are often the weakest link. In case of harsh vibration environments like military and automobile applications, joint failure mainly occurs due to the high stress incurred during extreme environmental conditions that lead to fatigue failures. This thesis aims to study the effects of real time vibration on area array packages (flip chips in particular) using acoustic micro imaging for through life monitoring of the solder joints. Since real time vibration on solder joints have not been studied before, the various steps for successful testing, through life monitoring of the solder joints and data analysis will be investigated and discussed. Based on automobile industry standards, a real time vibration profile was obtained with the help of Delphi experts, who are the industry collaborators of this project. Due to its strong capability to detect discontinuities within materials and interconnections, Acoustic Micro Imaging (AMI) also known as Scanning Acoustic Microscopy (CSAM) has been used to monitor the solder joints. This approach has not previously been used as an effective tool in monitoring solder joints through life performance in vibration testing. The research regime proposed in this thesis was to monitor the health of solder joints through ultrasound images from beginning to failure, and to see how cracks initiate and propagate in them. The effect of the relative position and orientation on the reliability of the solder joints and the flip chips in the PCB was also studied. The data collected was analysed using MATLAB. The results have shown that three types of solder joints- healthy, partially fractured or fractured are formed near the time of complete failure of a flip chip. When about 70- 80% of the flip chips are either partially fractured or fractured a flip chip is expected to fail. The mean pixel intensity and area change in the acoustic image of a partially fractured or fully fractured joint tends to be higher compared to a healthy joint. Crack initiation in a joint occurs at around 35-40% cycling and propagates linearly till 80-85% cycling after which a joint fails. A statistical analysis done on the solder joints showed that the intensity distribution of healthy joints follow a simple Gaussian distribution while that of partially fractured or fractured joint can only be represented by using a mixture of Gaussians. The solder joints near the board edges are the least reliable in a vibration environment. However, solder joints with back to back connections are more reliable than the ones placed in one sided orientation. The most reliable flip chip orientation in a vibration environment is the back to back connection with no offset which was actually found to be the least reliable in the case of thermal cycling. Based on the analysis of the results, a few design guidelines for flip chip layout and orientations in a PCB has also been proposed in this work

Investigation into Solder Joint Failure in Portable Electronics Subjected to Drop Impact

Ph.DDOCTOR OF PHILOSOPH

Modelling of the reliability of flip chip lead-free solder joints at high-temperature excursions

At high-temperature operations of electronic control devices, Tin-Silver-Copper (SnAgCu) alloy solder joints used to assemble the component of the devices are functioning at homologous temperature above 0.8. In such ambient temperatures, solder alloys have limited mechanical strength and will be sensitive to strain rate. The sensitivity of solder properties to creep/visco-plastic deformation increases the rate of accumulation of plastic damage in the alloy and decreases the number of cycles to failure (Nf) of the joints. Most untimely rupture of solder joints in high-temperature electronics (HTE) system usually culminates in colossal loss of resources and lives. Typical incidences are reported in recent automotive and aircraft crashes as well as the collapse of oil-well logging equipment. To increase the mean time to failure (MTTF) of solder joints in HTE, an in-depth understanding and accurate prediction of the response of solder joints to thermally induced plastic strain damage is crucial. This study concerns the prediction of the reliability of lead-free solder joints in a flip chip (FC) model FC48D6.3C457 which is mounted on a substrate and the assembly subjected to high-temperature excursions. The research investigates the effect of the high-temperature operations on reliability of the joints. In addition, the investigation examines the impact of control factors (component stand-off height (CSH), inter-metallic compound (IMC) thickness, number of thermal cycle and solder volume) on Nf of the joints. A model developed in the course of this investigation was employed to create the assembly solder joints architecture. The development of the model and creation of the bump profile involve a combination of both analytical and construction methods. The assembled package on a printed circuit board (PCB) was subjected to accelerated temperature cycle (ATC) employing IEC standard 60749-25 in parts. The cycled temperature range is between -38 oC and 157 oC. Deformation behaviour of SnAgCu alloy solder in the joints is captured using Anand’s visco-plasticity model and the response of other materials in the assembly were simulated with appropriate model. The results demonstrate that the reliability of solder joints operating at elevated temperatures is dependent on CSH, thickness of IMC and solder volume. It also shows that incorporating the IMC layer in the geometric models significantly improves the level of accuracy of fatigue life prediction to ± 22.5% (from the ± 25% which is currently generally accepted). The findings also illustrate that the magnitude of the predicted damage and fatigue life are functions of the number of ATC employed. The extensive set of results from the modelling study has demonstrated the need for incorporating the IMC layer in the geometric model to ensure greater accuracy in the prediction of solder joint service life. The technique developed for incorporating the IMC layer will be of value to R&D engineers and scientists engaged in high-temperature applications in the automotive, aerospace and oil-well logging sectors. The results have been disseminated through peer reviewed journals and also presentations at international conferences

Numerical analysis of lead-free solder joints: effects of thermal cycling and electromigration

To meet the requirements of miniaturization and multifunction in microelectronics, understanding of their reliability and performance has become an important research subject in order to characterise electronics served under various loadings. Along with the demands of the increasing miniaturization of electronic devices, various properties and the relevant thermo-mechanical-electrical response of the lead-free solder joints to thermal cycling and electro-migration become the critical factors, which affect the service life of microelectronics in different applications. However, due to the size and structure of solder interconnects in microelectronics, traditional methods based on experiments are not applicable in the evaluation of their reliability under complex joint loadings. This thesis presents an investigation, which is based on finite-element method, into the performance of lead-free solder interconnects under thermal fatigue and electro-migration, specifically in the areas as follows: (1) the investigation of thermal-mechanical performance and fatigue-life prediction of flip-chip package under different sizes to achieve a further understanding of IMC layer and size effects of a flip chip package under thermal cycling; (2) the establishment of a numerical method, simulating void-formation/crack-propagation based on the results of finite-element analysis, to allow the prediction of crack evolution and failure time for electro-migration reliability of solder bumps; (3) the establishment of a flow-based algorithm for combination effects of thermal-mechanical and electro-migration that was subsequent implemented in to an FE model to evaluate the reliability assessment of service lives associated with a flip chip package

EFFECT OF SURFACE FINISHES AND INTERMETALLICS ON THE RELIABILITY OF SnAgCu INTERCONNECTS

Power semiconductor devices are used in a wide range of applications. In these applications, power semiconductor devices are required to handle large currents and as a result they tend to dissipate large amounts of heat. In addition, the device and their attendant packages must be capable of withstanding power cycling for many years. Traditionally, devices have used high lead die attaches for high electrical and thermal conductivity. Now, with the drive in industry to replace lead-contained solder with lead-free solder alternatives, there is a drive to assess lead-free solder to use as the die attach in power device packages. This dissertation assesses the reliability of Sn3.5Ag0.8Cu lead-free die attach under accelerated power cycling conditions, especially the effect of surface finishes from the die and the substrate on die attach reliability because of the thin die attach thickness (<100mm), which is expected to increase the influence of intermetallics formed at the interfaces on the joint reliability. The main part of the thesis is to evaluate the power-cycle reliability of Sn3.5Ag0.8Cu die attach in power MOSFET modules subjected to power cycling. Accelerated power cycling tests, failure analysis, thermal transient analysis and thermo-mechanical modeling were conducted. 3D thermal analysis correlated an increase in the package thermal impedance to the amount of crack propagation and determined that crack initiation is the limiting process under power cycling. In the experiments, die tilt was observed and die attach cracks always occurred near the middle of the bond line on the side with thicker die attach. This is not addressed in typical thermo-mechanical simulations on solder joint reliability. Such simulations predicted that the thinner side exhibits higher stress than the thicker side and were expected to be easier to fail. Microstructural characterization provided evidences that microstructure of die attach changes with thickness. First, a higher Ag3Sn concentration was observed in the thinner die attach due to dissolution of Ag from backside die. Second, a more uniform distribution of Ag3Sn precipitates exists in the thinner die attach due to faster cooling. So a thinner Sn3.5Ag0.8Cu die attach is more resistant to fatigue failure even under higher stresses

Mechanics of Non Planar Interfaces in Flip-Chip Interconnects

With the continued proliferation of low cost, portable consumer electronic products with greater functionality, there is increasing demand for electronic packaging that is smaller, lighter and less expensive. Flip chip is an essential enabling technology for these products. The electrical connection between the chip I/O and substrate is achieved using conductive materials, such as solder, conductive epoxy, metallurgy bump (e.g., gold) and anisotropic conductive adhesives. The interconnect regions of flip-chip packages consists of highly dissimilar materials to meet their functional requirements. The mismatches in properties, contact morphology and crystal orientation at those material interfaces make them vulnerable to failure through delamination and crack growth under various loading patterns. This study encompasses contact between deformable bodies, bonding at the asperities and fracture properties at interfaces formed by the interconnects of flip-chip packages. This is achieved through experimentation and modeling at different length scales, to be able to capture the detailed microstructural features and contact mechanics at interfaces typically found in electronic systems

The durability of solder joints under thermo-mechanical loading; application to Sn-37Pb and Sn-3.8Ag-0.7Cu lead-free replacement alloy

Solder joints in electronic packages provide mechanical, electrical and thermal connections. Hence, their reliability is also a major concern to the electronic packaging industry. Ball Grid Arrays (BGAs) are a very common type of surface mount technology for electronic packaging. This work primarily addresses the thermo-mechanical durability of BGAs and is applied to the exemplar alloys; traditional leaded solder and a popular lead-free solder. Isothermal mechanical fatigue tests were carried out on 4-ball test specimens of the lead-free (Sn-3.8Ag-0.7Cu) and leaded (Sn-37Pb) solder under load control at room temperature, 35°C and 75°C. As well as this, a set of combined thermal and mechanical cycling tests were carried out, again under load control with the thermal cycles either at a different frequency from the mechanical cycles (not-in-phase) or at the same frequency (both in phase and out-of-phase). The microstructural evaluation of both alloys was investigated by carrying out a series of simulated ageing tests, coupled with detailed metallurgical analysis and hardness testing. The results were treated to produce stress-life, cyclic behaviour and creep curves for each of the test conditions. Careful calibration allowed the effects of substrate and grips to be accounted for and so a set of strain-life curves to be produced. These results were compared with other results from the literature taking into account the observations on microstructure made in the ageing tests. It is generally concluded that the TMF performance is better for the Sn-Ag-Cu alloy than for the Sn-Pb alloy, when expressed as stress-life curves. There is also a significant effect on temperature and phase for each of the alloys, the Sn-Ag-Cu being less susceptible to these effects. When expressed as strain life, the effects of temperature, phase and alloy type are much diminished. Many of these conclusions coincided with only parts of the literature and reasons for the remaining differences are advanced

Semiconductor Packaging

In semiconductor manufacturing, understanding how various materials behave and interact is critical to making a reliable and robust semiconductor package. Semiconductor Packaging: Materials Interaction and Reliability provides a fundamental understanding of the underlying physical properties of the materials used in a semiconductor package. By tying together the disparate elements essential to a semiconductor package, the authors show how all the parts fit and work together to provide durable protection for the integrated circuit chip within as well as a means for the chip to communicate with the outside world. The text also covers packaging materials for MEMS, solar technology, and LEDs and explores future trends in semiconductor packages

Damage Initiation and Evolution in Voided and Unvoided Lead Free Solder Joints Under Cyclic Thermo-Mechanical Loading

The effect of process-induced voids on the durability of Sn-Pb and Pb-free solder interconnects in electronic products is not clearly understood and researchers have reported conflicting findings. Studies have shown that depending on the size and location, voids are not always detrimental to reliability, and in fact, may sometimes even increase the durability of joints. This debate is more intensified in Pb-free solders; since voids are more common in Pb-free joints. Results of experimental studies are presented in this study to empirically explore the influence of voids on the durability of Ball Grid Array (BGA) Pb-free solder joints. In order to quantify the detailed influence of size, location, and volume fraction of voids, extensive modeling is conducted, using a continuum damage model (Energy Partitioning model), rather than the existing approaches, such as fracture mechanics, reported in the literature. The E-P approach is modified in this study by use of a successive initiation method, since depending on their location and size; voids may influence either the time to initiate cyclic fatigue damage or time to propagate fatigue damage, or both. Modeling results show competing interactions between void size and location, that results in a non-monotonic relationship between void size and durability. It also suggests that voids in general are not detrimental to reliability except when a large portion of the damage propagation path is covered with either a large void or with many small voids. In addition, this dissertation also addresses several fundamental issues in solder fatigue damage modeling. One objective is to use experimental data to identify the correct fatigue constants to be used when explicitly modeling fatigue damage propagation in Pb-free solders. Explicit modeling of damage propagation improves modeling accuracy across solder joints of vastly different architectures, since the joint geometry may have a strong influence on the ratio of initiation-life to propagation-life. Most solder fatigue models in the literature do not provide this capability since they predict failure based only on the damage accumulation rates during the first few cycles in the undamaged joint. Another objective is to incorporate into cyclic damage propagation models, the effect of material softening caused by cyclic micro-structural damage accumulation in Pb-free solder materials. In other words the model constants of the solder viscoplastic constitutive model are continuously updated with the help of experimental data, to include this cyclic softening effect as damage accumulates during the damage-propagation phase. The ability to model this damage evolution process increases the accuracy of durability predictions, and is not available in most current solder fatigue models reported in the literature. This mechanism-based microstructural damage evolution model, called the Energy Partitioning Damage Evolution (EPDE) model is developed and implemented in Finite Element Analysis of solder joints with the successive initiation technique and the results are provided here. Experimental results are used as guidance to calibrate the Energy Partitioning fatigue model constants, for use in successive initiation modeling with and without damage evolution. FEA results show 15% difference between the life predicted by averaging technique and successive initiation. This difference could significantly increase in the case of long joints such as thermal pads or die-attach, hence validating the use of successive initiation in these cases. The difference between using successive initiation with and without damage evolution is about 10%. Considering the small amount of effort that has to be made to update the constitutive properties for progressive degradation, it is recommended that softening be included whenever damage propagation needs to be explicitly modeled. However the damage evolution exponents and the corresponding E-P model constants obtained in this study, using successive initiation with damage evolution, are partially dependent on the specimen geometry. Hence, these constants may have to be re-calibrated for other geometries

NANO-PARTICLE REINFORCED SOLDERS FOR MICROELECTRONIC INTERCONNECT APPLICATIONS

Ph.DDOCTOR OF PHILOSOPH