Towards Structural Testing of Superconductor Electronics

Many of the semiconductor technologies are already\ud facing limitations while new-generation data and\ud telecommunication systems are implemented. Although in\ud its infancy, superconductor electronics (SCE) is capable of\ud handling some of these high-end tasks. We have started a\ud defect-oriented test methodology for SCE, so that reliable\ud systems can be implemented in this technology. In this\ud paper, the details of the study on the Rapid Single-Flux\ud Quantum (RSFQ) process are presented. We present\ud common defects in the SCE processes and corresponding\ud test methodologies to detect them. The (measurement)\ud results prove that we are able to detect possible random\ud defects for statistical purposes in yield analysis. This\ud paper also presents possible test methodologies for RSFQ\ud circuits based on defect oriented testing (DOT)

Design of lightning protection for a full-authority digital engine control

The steps and procedures are described which are necessary to achieve a successful lightning-protection design for a state-of-the-art Full-Authority Digital Engine Control (FADEC) system. The engine and control systems used as examples are fictional, but the design and verification methods are real. Topics discussed include: applicable airworthiness regulation, selection of equipment transient design and control levels for the engine/airframe and intra-engine segments of the system, the use of cable shields, terminal-protection devices and filter circuits in hardware protection design, and software approaches to minimize upset potential. Shield terminations, grounding, and bonding are also discussed, as are the important elements of certification and test plans, and the role of tests and analyses. Also included are examples of multiple-stroke and multiple-burst testing. A review of design pitfalls and challenges, and status of applicable test standards such as RTCA DO-160, Section 22, are presented

Sensors and Methods for Railway Signalling Equipment Monitoring

Signalling upgrade projects that have been installed in equipment rooms in the recent past have limited capability to monitor performance of certain types of external circuits. To modify the equipment rooms on the commissioned railway would prove very expensive to implement and would be unacceptable in terms of delays caused to passenger services due to re-commissioning circuits after modification, to comply with rail signalling standards. The use of magnetoresistive sensors to provide performance data on point circuit operation and point operation is investigated. The sensors are bench tested on their ability to measure current in a circuit in a non-intrusive manner. The effect of shielding on the sensor performance is tested and found to be significant. The response of the sensors with various levels of amplification produces linear responses across a range of circuit gain. The output of the sensor circuit is demonstrated for various periods of interruption of conductor current. A three-axis accelerometer is mounted on a linear actuator to demonstrate the type of output expected from similar sensors mounted on a set of points. Measurements of current in point detection circuits and acceleration forces resulting from vibration of out of tolerance mechanical assemblies can provide valuable information on performance and possible threats to safe operation of equipment. The sensors seem capable of measuring the current in a conductor with a comparatively high degree of sensitivity. There is development work required on shielding the sensor from magnetic fields other than those being measured. The accelerometer work is at a demonstration level and requires development. The future testing work with accelerometers should be at a facility where multiple point moves can be made; with the capability to introduce faults to the point mechanisms. Methods can then be developed for analysis of the vibration signatures produced by the various faults

Improved micro-contact resistance model that considers material deformation, electron transport and thin film characteristics

This paper reports on an improved analytic model forpredicting micro-contact resistance needed for designing microelectro-mechanical systems (MEMS) switches. The originalmodel had two primary considerations: 1) contact materialdeformation (i.e. elastic, plastic, or elastic-plastic) and 2) effectivecontact area radius. The model also assumed that individual aspotswere close together and that their interactions weredependent on each other which led to using the single effective aspotcontact area model. This single effective area model wasused to determine specific electron transport regions (i.e. ballistic,quasi-ballistic, or diffusive) by comparing the effective radius andthe mean free path of an electron. Using this model required thatmicro-switch contact materials be deposited, during devicefabrication, with processes ensuring low surface roughness values(i.e. sputtered films). Sputtered thin film electric contacts,however, do not behave like bulk materials and the effects of thinfilm contacts and spreading resistance must be considered. Theimproved micro-contact resistance model accounts for the twoprimary considerations above, as well as, using thin film,sputtered, electric contact

Aircraft electromagnetic compatibility

Illustrated are aircraft architecture, electromagnetic interference environments, electromagnetic compatibility protection techniques, program specifications, tasks, and verification and validation procedures. The environment of 400 Hz power, electrical transients, and radio frequency fields are portrayed and related to thresholds of avionics electronics. Five layers of protection for avionics are defined. Recognition is given to some present day electromagnetic compatibility weaknesses and issues which serve to reemphasize the importance of EMC verification of equipment and parts, and their ultimate EMC validation on the aircraft. Proven standards of grounding, bonding, shielding, wiring, and packaging are laid out to help provide a foundation for a comprehensive approach to successful future aircraft design and an understanding of cost effective EMC in an aircraft setting

Smart Recloser

The goal of this project was to develop an intelligent recloser system that is able to differentiate between a temporary and a persistent fault, and then take proper action. The intended use of this system is to increase reliability and energy quality. The system was realized by using a non-invasive method to monitor the soundness of the line. Through signal processing, this information is converted into logic that a microprocessor can use to control the recloser

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers

Preliminary tests of vulnerability of typical aircraft electronics to lightning-induced voltages

Tests made on two pieces of typical aircraft electronics equipment to ascertain their vulnerability to simulated lightning-induced transient voltages representative of those which might occur in flight when the aircraft is struck by lightning were conducted. The test results demonstrated that such equipment can be interfered with or damaged by transient voltages as low as 21 volts peak. Greater voltages can cause failure of semiconductor components within the equipment. The results emphasize a need for establishment of coordinated system susceptibility and component vulnerability criteria to achieve lightning protection of aerospace electrical and electronic systems

SINGLE EVENT UPSET DETECTION IN FIELD PROGRAMMABLE GATE ARRAYS

The high-radiation environment in space can lead to anomalies in normal satellite operation. A major cause of concern to spacecraft-designers is the single event upset (SEU). SEUs can result in deviations from expected component behavior and are capable of causing irreversible damage to hardware. In particular, Field Programmable Gate Arrays (FPGAs) are known to be highly susceptible to SEUs. Radiation-hardened versions of such devices are associated with an increase in power consumption and cost in addition to being technologically inferior when compared to contemporary commercial-off-the-shelf (COTS) parts. This thesis consequently aims at exploring the option of using COTS FPGAs in satellite payloads. A framework is developed, allowing the SEU susceptibility of such a device to be studied. SEU testing is carried out in a software-simulated fault environment using a set of Java classes called JBits. A radiation detector module, to measure the radiation backdrop of the device, is also envisioned as part of the final design implementation