Spread spectrum communication link using surface wave devices

A fast lock-up, 8-MHz bandwidth 8,000 bit per second data rate spread spectrum communication link breadboard is described that is implemented using surface wave devices as the primary signal generators and signal processing elements. It uses surface wave tapped delay lines in the transmitter to generate the signals and in the receiver to detect them. The breadboard provides a measured processing gain for Gaussian noise of 31.5 dB which is within one dB of the theoretical optimum. This development demonstrates that spread spectrum receivers implemented with surface wave devices have sensitivities and complexities comparable to those of serial correlation receivers, but synchronization search times which are two to three orders of magnitude smaller

ANS hard X-ray experiment development program

The hard X-ray (HXX) experiment is one of three experiments included in the Dutch Astronomical Netherlands Satellite, which was launched into orbit on 30 August 1974. The overall objective of the HXX experiment is the detailed study of the emission from known X-ray sources over the energy range 1.5-30keV. The instrument is capable of the following measurements: (1) spectral content over the full energy range with an energy resolution of approximately 20% and time resolution down to 4 seconds; (2) source time variability down to 4 milliseconds; (3) silicon emission lines at 1.86 and 2.00keV; (4) source location to a limit of one arc minute in ecliptic latitude; and (5) spatial structure with angular resolution of the arc minutes. Scientific aspects of experiment, engineering design and implementation of the experiment, and program history are included

emiT: an apparatus to test time reversal invariance in polarized neutron decay

We describe an apparatus used to measure the triple-correlation term (\D \hat{\sigma}_n\cdot p_e\times p_\nu) in the beta-decay of polarized neutrons. The \D-coefficient is sensitive to possible violations of time reversal invariance. The detector has an octagonal symmetry that optimizes electron-proton coincidence rates and reduces systematic effects. A beam of longitudinally polarized cold neutrons passes through the detector chamber, where a small fraction beta-decay. The final-state protons are accelerated and focused onto arrays of cooled semiconductor diodes, while the coincident electrons are detected using panels of plastic scintillator. Details regarding the design and performance of the proton detectors, beta detectors and the electronics used in the data collection system are presented. The neutron beam characteristics, the spin-transport magnetic fields, and polarization measurements are also described.Comment: 15 pages, 13 figure

Effect of Clock and Power Gating on Power Distribution Network Noise in 2D and 3D Integrated Circuits

In this work, power supply noise contribution, at a particular node on the power grid, from clock/power gated blocks is maximized at particular time and the synthetic gating patterns of the blocks that result in the maximum noise is obtained for the interval 0 to target time. We utilize wavelet based analysis as wavelets are a natural way of characterizing the time-frequency behavior of the power grid. The gating patterns for the blocks and the maximum supply noise at the Point of Interest at the specified target time obtained via a Linear Programming (LP) formulation (clock gating) and Genetic Algorithm based problem formulation (Power Gating)

Development and evaluation of a fault-tolerant multiprocessor (FTMP) computer. Volume 1: FTMP principles of operation

The basic organization of the fault tolerant multiprocessor, (FTMP) is that of a general purpose homogeneous multiprocessor. Three processors operate on a shared system (memory and I/O) bus. Replication and tight synchronization of all elements and hardware voting is employed to detect and correct any single fault. Reconfiguration is then employed to repair a fault. Multiple faults may be tolerated as a sequence of single faults with repair between fault occurrences

AROD test model hardware, volume 2 Final report

Engineering design data on vehicle-borne subsystems of airborne range and orbit determination syste

High-performance and Low-power Clock Network Synthesis in the Presence of Variation.

Semiconductor technology scaling requires continuous evolution of all aspects of physical design of integrated circuits. Among the major design steps, clock-network synthesis has been greatly affected by technology scaling, rendering existing methodologies inadequate. Clock routing was previously sufficient for smaller ICs, but design difficulty and structural complexity have greatly increased as interconnect delay and clock frequency increased in the 1990s. Since a clock network directly influences IC performance and often consumes a substantial portion of total power, both academia and industry developed synthesis methodologies to achieve low skew, low power and robustness from PVT variations. Nevertheless, clock network synthesis under tight constraints is currently the least automated step in physical design and requires significant manual intervention, undermining turn-around-time. The need for multi-objective optimization over a large parameter space and the increasing impact of process variation make clock network synthesis particularly challenging. Our work identifies new objectives, constraints and concerns in the clock-network synthesis for systems-on-chips and microprocessors. To address them, we generate novel clock-network structures and propose changes in traditional physical-design flows. We develop new modeling techniques and algorithms for clock power optimization subject to tight skew constraints in the presence of process variations. In particular, we offer SPICE-accurate optimizations of clock networks, coordinated to reduce nominal skew below 5 ps, satisfy slew constraints and trade-off skew, insertion delay and power, while tolerating variations. To broaden the scope of clock-network-synthesis optimizations, we propose new techniques and a methodology to reduce dynamic power consumption by 6.8%-11.6% for large IC designs with macro blocks by integrating clock network synthesis within global placement. We also present a novel non-tree topology that is 2.3x more power-efficient than mesh structures. We fuse several clock trees to create large-scale redundancy in a clock network to bridge the gap between tree-like and mesh-like topologies. Integrated optimization techniques for high-quality clock networks described in this dissertation strong empirical results in experiments with recent industry-released benchmarks in the presence of process variation. Our software implementations were recognized with the first-place awards at the ISPD 2009 and ISPD 2010 Clock-Network Synthesis Contests organized by IBM Research and Intel Research.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/89711/1/ejdjsy_1.pd

Solar gamma ray monitor for OSO-H (0.3-10 MeV)

A gamma ray experiment to be flown aboard the OSO-7 spacecraft is described along with a history of the development of the experiment, a description of the gamma ray detector and its operation, and a short preliminary review of the scientific information obtained during the instruments' lifetime. The gamma ray detector operated an average of 18 hours a day for approximately 15 months. The majority of the data was collected in the solar and antisolar direction, but data at right angles to the spacecraft-sun line was also accumulated. In all, at least two full scans of the celestial sphere were completed

High performance IC clock networks with grid and tree topologies

In this dissertation, an essential step in the integrated circuit (IC) physical design flow—the clock network design—is investigated. Clock network design entailsa series of computationally intensive, large-scale design and optimization tasks for the generation and distribution of the clock signal through different topologies. The lack or inefficacy of the automation for implementing high performance clock networks, especially for low-power, high speed and variation-aware implementations, is the main driver for this research. The synthesis and optimization methods for the two most commonly used clock topologies in IC design—the grid topology and the tree topology—are primarily investigated.The clock mesh network, which uses the grid topology, has very low skew variation at the cost of high power dissipation. Two novel clock mesh network designmethodologies are proposed in this dissertation in order to reduce the power dissipation. These are the first methods known in literature that combine clock meshsynthesis with incremental register placement and clock gating for power saving purposes. The application of the proposed automation methods on the emerging resonant rotary clocking technology, which also has the grid topology, is investigated in this dissertation as well.The clock tree topology has the advantage of lower power dissipation compared to other traditional clock topologies (e.g. clock mesh, clock spine, clock tree with cross links) at the cost of increased performance degradation due to on-chip variations. A novel clock tree buffer polarity assignment flow is proposed in this dissertation in order to reduce these effects of on-chip variations on the clock tree topology. The proposed polarity assignment flow is the first work that introduces post-silicon, dynamic reconfigurability for polarity assignment, enabling clock gating for low power operation of the variation-tolerant clock tree networks.Ph.D., Electrical Engineering -- Drexel University, 201