Design of Asynchronous Viterbi Decoder for Low Power Applications

In todays digital communication systems, convolutional codes are broadly used in channel coding techniques.The viterbi decoder due to its high performance is commonly used for decoding the convolutional codes. Fast developments in the communication field have created a rising demand for high speed and low power viterbi decoders with long battery life and low weight. Despite the significant progress in the last decade, the problem of power dissapation in the viterbi decoders still remains challenging and requires further technical solutions.In this paper we proposed the methods for survivor path storage and decoding as Register Exchange Method (REM) and Hybrid Register Exchange method (HREM). REM cosumes large power and area, due to huge switching activity.The problem of switching activity of Viterbi decoder can be reduced by combining Traceback and REM and the method called Hybrid Register Exchange Method (HREM). The Viterbi decoder is designed using REM and HREM and simulated on Quartus tool and power is calculated on Power play power analyzer. As the switching activity is reduced in HREM as compared to REM the viterbi decoder achieves reduction in power in HREM as compared with REM .For further reduction in power of viterbi decoder we proposed asynchronous techniques like handshaking protocol. Here we designed the Asynchronous Viterbi decoder by using 2 phase dual rail encoding (LEDR)

A Low Power Asynchronous Viterbi Decoder using LEDR Encoding

With the consumer demand for increased content and as a result, increasing high data bandwidth continuing to drive communications systems, coding for error control has become extraordinarily important. One way to improve the Bit Error Rate (BER), while maintaining high data reliability, is to use an error correction technique like the Viterbi algorithm. Originally conceived by Andrew Viterbi as an error-correction scheme for noisy digital communication, the Viterbi algorithm provides an efficient method for Forward Error Correction (FEC) that improves channel reliability. Today, it is used in many digital communications systems in applications as diverse as LTE Physical Downlink Control Channel (PDCCH), CDMA and GSM, digital cellular, dial up modems, satellite, deep-space communications, and 802.11 wireless LANs. Though it is useful for error correction it dissipates large power. A lot many researches were carried out at architectural as well as algorithmic level to optimize the ACS (Add compare and Select) unit and Survival Memory Management in Synchronous Viterbi Decoders. But still there is a problem of power dissipation which requires more technical solutions. Due to requirements of high speed, low power, low weight and long battery life a low power Viterbi decoders has a great demand in the communication field. This paper proposed the method for survivor path storage and decoding as Minimum Transition Hybrid Register Exchange Method along with handshaking protocol as Level Encoded dual rail (LEDR) encoding to make the system asynchronous. The whole system has been designed on algorithmic level and Simulation is done on Xilinx Tool for Asynchronous Viterbi Decoder using MTHREM

Design of Asynchronous Viterbi Decoder using Bundled Data Protocol for Low Power Consumption

Abstract: This paper proposes a review on the designing of Asynchronous Viterbi Decoder. In order to reduce the power consumption and increase the speed, it is necessary to design Asynchronous Viterbi Decoder. Therefore, the aim is to design Asynchronous Viterbi Decoder by using handshaking protocol. This paper focuses on Bundled data protocol to design Asynchronous Viterbi Decoder. This paper also describes study of various units of Viterbi decoder. Viterbi decoders employed in digital wireless communications are complex and dissipiate large power. Asynchronous Viterbi Decoder have significant role in terms of performance because they saves power through not having to generate or distribute a global clock. Instead, timing between blocks is performed by local handshake signals. Asynchronous Viterbi decoders are used in wide range of applications i.e. in Wireless Communications, Digital Television broadcast, Largest applications in cell phones, Pattern recognition, Speech recognition CD ROMS and Magnetic disks etc. In Mobile station Baseband Modem, Viterbi Decoder consumes more than One-third of chip area and power dissipation of the baseband modem. Power efficiency can be increased if total power dissipation is decreased. Battery operated systems required Low power consumption. Asynchronous designs are inherently data driven and are active only when doing useful work, enabling significant savings in power and operating at the average speed of all components

Unified turbo/LDPC code decoder architecture for deep-space communications

Deep-space communications are characterized by extremely critical conditions; current standards foresee the usage of both turbo and low-density-parity-check (LDPC) codes to ensure recovery from received errors, but each of them displays consistent drawbacks. Code concatenation is widely used in all kinds of communication to boost the error correction capabilities of single codes; serial concatenation of turbo and LDPC codes has been recently proven effective enough for deep space communications, being able to overcome the shortcomings of both code types. This work extends the performance analysis of this scheme and proposes a novel hardware decoder architecture for concatenated turbo and LDPC codes based on the same decoding algorithm. This choice leads to a high degree of datapath and memory sharing; postlayout implementation results obtained with complementary metal-oxide semiconductor (CMOS) 90 nm technology show small area occupation (0.98 mm 2 ) and very low power consumption (2.1 mW)

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz

VLSI decoding architectures: flexibility, robustness and performance

Stemming from previous studies on flexible LDPC decoders, this thesis work has been mainly focused on the development of flexible turbo and LDPC decoder designs, and on the narrowing of the power, area and speed gap they might present with respect to dedicated solutions. Additional studies have been carried out within the field of increased code performance and of decoder resiliency to hardware errors. The first chapter regroups several main contributions in the design and implementation of flexible channel decoders. The first part concerns the design of a Network-on-Chip (NoC) serving as an interconnection network for a partially parallel LDPC decoder. A best-fit NoC architecture is designed and a complete multi-standard turbo/LDPC decoder is designed and implemented. Every time the code is changed, the decoder must be reconfigured. A number of variables influence the duration of the reconfiguration process, starting from the involved codes down to decoder design choices. These are taken in account in the flexible decoder designed, and novel traffic reduction and optimization methods are then implemented. In the second chapter a study on the early stopping of iterations for LDPC decoders is presented. The energy expenditure of any LDPC decoder is directly linked to the iterative nature of the decoding algorithm. We propose an innovative multi-standard early stopping criterion for LDPC decoders that observes the evolution of simple metrics and relies on on-the-fly threshold computation. Its effectiveness is evaluated against existing techniques both in terms of saved iterations and, after implementation, in terms of actual energy saving. The third chapter portrays a study on the resilience of LDPC decoders under the effect of memory errors. Given that the purpose of channel decoders is to correct errors, LDPC decoders are intrinsically characterized by a certain degree of resistance to hardware faults. This characteristic, together with the soft nature of the stored values, results in LDPC decoders being affected differently according to the meaning of the wrong bits: ad-hoc error protection techniques, like the Unequal Error Protection devised in this chapter, can consequently be applied to different bits according to their significance. In the fourth chapter the serial concatenation of LDPC and turbo codes is presented. The concatenated FEC targets very high error correction capabilities, joining the performance of turbo codes at low SNR with that of LDPC codes at high SNR, and outperforming both current deep-space FEC schemes and concatenation-based FECs. A unified decoder for the concatenated scheme is subsequently propose