Radiation safety based on the sky shine effect in reactor

In the reactor operation, neutrons and gamma rays are the most dominant radiation. As protection, lead and concrete shields are built around the reactor. However, the radiation can penetrate the water shielding inside the reactor pool. This incident leads to the occurrence of sky shine where a physical phenomenon of nuclear radiation sources was transmitted panoramic that extends to the environment. The effect of this phenomenon is caused by the fallout radiation into the surrounding area which causes the radiation dose to increase. High doses of exposure cause a person to have stochastic effects or deterministic effects. Therefore, this study was conducted to measure the radiation dose from sky shine effect that scattered around the reactor at different distances and different height above the reactor platform. In this paper, the analysis of the radiation dose of sky shine effect was measured using the experimental metho

Design and implementation of the subsystem subject to emission of multicomponent high-frequency signals to ensure its reliability

Telecommunication systems, especially digital ones, are mostly known to be immune to noise given their extensive range of applications. This study aimed to investigate the methods and tools used for the analysis of multicomponent signals input to high-frequency digital subsystems, including the analysis of changes in its electrical behavior. This research mainly focuses on analyzing a high-frequency telecommunication subsystem, recording the results, investigating the system behavior against signals with different amplitudes and phases, detecting the received signals, and measuring the phase differences. The study extended the mono-component signals to multi-component signals and accurately extracted the statistical signal specifications using analytic signals in the time-frequency domain. To this end, a method was proposed based on the switch matrix to relate the different components and parameters, and also a mathematical model based on the state-space equations was employed to evaluate the nonlinear system modes. Given that the decoupling of measurement parameters is a problem to be tackled from multiple aspects, the costs and test durations were also taken into calculations in addition to considering all the detection methods for interference signals, reliability and time under test

A Low-Overhead Method for Pre-bond Test of Resonant 3-D Clock Distribution Networks

Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low power alternatives to con- ventional clock distribution schemes. These networks utilize ad- ditional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. Test is another complex task for 3-D ICs, where pre-bond test is a prerequisite. Contactless test has been considered as an alternative for conventional test methods. This paper, consequently, introduces a design method- ology for resonant 3-D clock networks that supports wireless pre- bond testing through the use of inductive links. By employing the inductors comprising the LC tanks of the resonant clock net- works as the receiver circuit for the links, the need for additional circuits and/or interconnect resources during pre-bond test is essentially eliminated. The proposed technique produces low power and pre-bond testable 3-D clock distribution networks. Simulation results indicate 98.5% and 99% decrease in the area overhead and power consumed by the contactless testing method as compared to existing methods

공정변이를 고려한 3차원 집적 회로 설계 및 패키징 기법

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 김태환.As CMOS scaling down, The control of variation in chip performance (i.e. speed and power) becomes highly important to improve the chip yield. The increased variation of chip performance demands additional design efforts such as the increase of guard-band or longer design turnaround time (TAT), which cause degradation of both chip performance and economic profit. Meanwhile, through-silicon via (TSV) based 3D technology has been regarded as the promising solution for long interconnect wire and huge die size problem. Since a 3D IC is manufactured by stacking multiple dies which are fabricated in different wafers, integration of the dies that have far different process characteristic can enlarge the difference of device performance on different dies within a single chip. In this dissertation, we analyze the effect of on-package (within-chip) variation on 3D IC and presents effective methods to mitigate the onpackage variation. First, a parametric yield improvement method is presented to resolve the mismatches of dies having different process characteristic. Comprehensive 3D integration algorithms considering post-silicon tuning technique is developed for the multi-layered 3D IC. Then, we show that a careful clock edge embedding in 3D clock tree can greatly reduce the impact of on-package variation on 3D clock skew and propose a two-step solution for the problem of on-package variation-aware layer embedding in 3D clock tree synthesis. In summary, this dissertation presents effective 3D integration method and 3D clock tree synthesis algorithm for process-variation tolerant 3D IC designs.Abstract i Contents ii List of Figures iv List of Tables vii 1 Introduction 1 1.1 Process Variation in 3D ICs . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Contributions of This Dissertation . . . . . . . . . . . . . . . . . . . 6 2 Post-silicon Tuning Aware Die/WaferMatching Algorithms for Enhancing Parametric Yield of 3D IC Design 7 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 The Die-to-Die Matching Problem and Proposed Algorithm Considering Body Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.1 Motivation and Problem Definition . . . . . . . . . . . . . . 13 2.3.2 The Proposed Die-to-Die Matching Algorithm . . . . . . . . 15 2.4 TheWafer-to-Wafer Matching Problem and Proposed Algorithm Considering Body Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4.1 Problem Definition and The Proposed Wafer-to-Wafer Matching Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3 Edge Layer Embedding Algorithm for Mitigating On-Package Variation in 3D Clock Tree Synthesis 32 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.2 Problem Definitions and Motivation . . . . . . . . . . . . . . . . . . 35 3.3 The Proposed Algorithm for On-Package Variation Aware Edge Embedding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.1 Algorithm for Maximizing Layer Sharing of Edges . . . . . . 39 3.3.2 Refinement: Partial Edge Embedding on Layers . . . . . . . . 47 3.3.3 Clock Tree Routing and Buffer Insertion . . . . . . . . . . . . 49 3.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4 Conclusion 64 4.1 Chapter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.2 Chapter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Abstract in Korean 72Docto

Integrating specification and test requirements as constraints in verification strategies for 2D and 3D analog and mixed signal designs

Analog and Mixed Signal (AMS) designs are essential components of today’s modern Integrated Circuits (ICs) used in the interface between real world signals and the digital world. They present, however, significant verification challenges. Out-of-specification failures in these systems have steadily increased, and have reached record highs in recent years. Increasing design complexity, incomplete/wrong specifications (responsible for 47% of all non functional ICs) as well as additional challenges faced when testing these systems are obvious reasons. A particular example is the escalating impact of realistic test conditions with respect to physical (interface between the device under test (DUT) and the test instruments, input-signal conditions, input impedance, etc.), functional (noise, jitter) and environmental (temperature) constraints. Unfortunately, the impact of such constraints could result in a significant loss of performance and design failure even if the design itself was flawless. Current industrial verification methodologies, each addressing specific verification challenges, have been shown to be useful for detecting and eliminating design failures. Nevertheless, decreases in first pass silicon success rates illustrate the lack of cohesive, efficient techniques to allow a predictable verification process that leads to the highest possible confidence in the correctness of AMS designs. In this PhD thesis, we propose a constraint-driven verification methodology for monitoring specifications of AMS designs. The methodology is based on the early insertion of test(s) associated with each design specification. It exploits specific constraints introduced by these planned tests as well as by the specifications themselves, as they are extracted and used during the verification process, thus reducing the risk of costly errors caused by incomplete, ambiguous or missing details in the specification documents. To fully analyze the impact of these constraints on the overall AMS design behavior, we developed a two-phase algorithm that automatically integrates them into the AMS design behavioral model and performs the specifications monitoring in a Matlab simulation environment. The effectiveness of this methodology is demonstrated for two-dimensional (2D) and three-dimensional (3D) ICs. Our results show that our approach can predict out-of-specification failures, corner cases that were not covered using previous verification methodologies. On one hand, we show that specifications satisfied without specification and test-related constraints have failed in the presence of these additional constraints. On the other hand, we show that some specifications may degrade or even cannot be verified without adding specific specification and test-related constraints

Signaling in 3-D integrated circuits, benefits and challenges

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuits provide a potent approach to enhance the performance and integrate diverse functions within amulti-plane stack. Clock networks consume a great portion of the power dissipated in a circuit. Therefore, designing a low-power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Synchronization issues can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics. Consequently, designing low power clock networks for 3-D circuits is an important issue. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In this research, a design method to apply resonant clocking to synthesized clock trees is proposed. Manufacturing processes for 3-D circuits include some additional steps as compared to standard CMOS processes which makes 3-D circuits more susceptible to manufacturing defects and lowers the overall yield of the bonded 3-D stack. Testing is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Pre-bond testability, in turn, presents new challenges to 3-D clock network design primarily due to the incomplete clock distribution networks prior to the bonding of the planes. A design methodology of resonant 3-D clock networks that support wireless pre-bond testing is introduced. To efficiently address this issue, inductive links are exploited to wirelessly transmit the clock signal to the disjoint resonant clock networks. The inductors comprising the LC tanks are used as the receiver circuit for the links, essentially eliminating the need for additional circuits and/or interconnect resources during pre-bond test. Recent FPGAs are quite complex circuits which provide reconfigurablity at the cost of lower performance and higher power consumption as compared to ASIC circuits. Exploiting a large number of programmable switches, routing structures are mainly responsible for performance degradation in FPAGs. Employing 3-D technology can providemore efficient switches which drastically improve the performance and reduce the power consumption of the FPGA. RRAM switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. Along with the configurable switches, buffers are the other important element of the FPGAs routing structure. Different characteristics of RRAM switches change the properties of signal paths in RRAM-based FPGAs. The on resistance of RRAMswitches is considerably lower than CMOS pass gate switches which results in lower RC delay for RRAM-based routing paths. This different nature in critical path and signal delay in turn affect the need for intermediate buffers. Thus the buffer allocation should be reconsidered. In the last part of this research, the effect of intermediate buffers on signal propagation delay is studied and a modified buffer allocation scheme for RRAM-based FPGA routing path is proposed

Méthodologies de conception ASIC pour des systèmes sur puce 3D hétérogènes à base de réseaux sur puce 3D

Dans cette thèse, nous étudions les architectures 3D NoC grâce à des implémentations de conception physiques en utilisant la technologie 3D réel mis en oeuvre dans l'industrie. Sur la base des listes d'interconnexions en déroute, nous procédons à l'analyse des performances d'évaluer le bénéfice de l'architecture 3D par rapport à sa mise en oeuvre 2D. Sur la base du flot de conception 3D proposé en se concentrant sur la vérification temporelle tirant parti de l'avantage du retard négligeable de la structure de microbilles pour les connexions verticales, nous avons mené techniques de partitionnement de NoC 3D basé sur l'architecture MPSoC y compris empilement homogène et hétérogène en utilisant Tezzaron 3D IC technlogy. Conception et mise en oeuvre de compromis dans les deux méthodes de partitionnement est étudiée pour avoir un meilleur aperçu sur l'architecture 3D de sorte qu'il peut être exploitée pour des performances optimales. En utilisant l'approche 3D homogène empilage, NoC topologies est explorée afin d'identifier la meilleure topologie entre la topologie 2D et 3D pour la mise en œuvre MPSoC 3D sous l'hypothèse que les chemins critiques est fondée sur les liens inter-routeur. Les explorations architecturales ont également examiné les différentes technologies de traitement. mettant en évidence l'effet de la technologie des procédés à la performance d'architecture 3D en particulier pour l'interconnexion dominant du design. En outre, nous avons effectué hétérogène 3D d'empilage pour la mise en oeuvre MPSoC avec l'approche GALS de style et présenté plusieurs analyses de conception physiques connexes concernant la conception 3D et la mise en œuvre MPSoC utilisant des outils de CAO 2D. Une analyse plus approfondie de l'effet microbilles pas à la performance de l'architecture 3D à l'aide face-à-face d'empilement est également signalé l'identification des problèmes et des limitations à prendre en considération pendant le processus de conception.In this thesis, we study the exploration 3D NoC architectures through physical design implementations using real 3D technology used in the industry. Based on the proposed 3D design flow focusing on timing verification by leveraging the benefit of negligible delay of microbumps structure for vertical connections, we have conducted partitioning techniques for 3D NoC-based MPSoC architecture including homogeneous and heterogeneous stacking using Tezzaron 3D IC technlogy. Design and implementation trade-off in both partitioning methods is investigated to have better insight about 3D architecture so that it can be exploited for optimal performance. Using homogeneous 3D stacking approach, NoC architectures are explored to identify the best topology between 2D and 3D topology for 3D MPSoC implementation. The architectural explorations have also considered different process technologies highlighting the wire delay effect to the 3D architecture performance especially for interconnect-dominated design. Additionally, we performed heterogeneous 3D stacking of NoC-based MPSoC implementation with GALS style approach and presented several physical designs related analyses regarding 3D MPSoC design and implementation using 2D EDA tools. Finally we conducted an exploration of 2D EDA tool on different 3D architecture to evaluate the impact of 2D EDA tools on the 3D architecture performance. Since there is no commercialize 3D design tool until now, the experiment is important on the basis that designing 3D architecture using 2D EDA tools does not have a strong and direct impact to the 3D architecture performance mainly because the tools is dedicated for 2D architecture design.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Modeling and Design Techniques for 3-D ICs under Process, Voltage, and Temperature Variations

Three-dimensional (3-D) integration is a promising solution to further enhance the density and performance of modern integrated circuits (ICs). In 3-D ICs, multiple dies (tiers or planes) are vertically stacked. These dies can be designed and fabricated separately. In addition, these dies can be fabricated in different technologies. The effect of different sources of variations on 3-D circuits, consequently, differ from 2-D ICs. As technology scales, these variations significantly affect the performance of circuits. Therefore, it is increasingly important to accurately and efficiently model different sources of variations in 3-D ICs. The process, voltage, and temperature variations in 3-D ICs are investigated in this dissertation. Related modeling and design techniques are proposed to design a robust 3-D IC. Process variations in 3-D ICs are first analyzed. The effect of process variations on synchronization and 3-D clock distribution networks, is carefully studied. A novel statistical model is proposed to describe the timing variation in 3-D clock distribution networks caused by process variations. Based on this model, different topologies of 3-D clock distribution networks are compared in terms of skew variation. A set of guidelines is proposed to design 3-D clock distribution networks with low clock uncertainty. Voltage variations are described by power supply noise. Power supply noise in 3-D ICs is investigated considering different characteristics of potential 3-D power grids in this thesis. A new algorithm is developed to fast analyze the steady-state IR-drop in 3-D power grids. The first droop of power supply noise, also called resonant supply noise, is usually the deepest voltage drop in power distribution networks. The effect of resonant supply noise on 3-D clock distribution networks is investigated. The combined effect of process variations and power supply noise is modeled by skitter consisting of both skew and jitter. A novel statistical model of skitter is proposed. Based on this proposed model and simulation results, a set of guidelines has been proposed to mitigate the negative effect of process and voltage variations on 3-D clock distribution networks. Thermal issues in 3-D ICs are considered by carefully modeling thermal through silicon vias (TTSVs) in this dissertation. TTSVs are vertical vias which do not carry signals, dedicated to facilitate the propagation of heat to reduce the temperature of 3-D ICs. Two analytic models are proposed to describe the heat transfer in 3-D circuits related to TTSVs herein, providing proper closed-form expressions for the thermal resistance of the TTSVs. The effect of different physical and geometric parameters of TTSVs on the temperature of 3-D ICs is analyzed. The proposed models can be used to fast and accurately estimate the temperature to avoid the overuse of TTSVs occupying a large portion of area. A set of models and design techniques is proposed in this dissertation to describe and mitigate the deleterious effects of process, voltage, and temperature variations in 3-D ICs. Due to the continuous shrink in the feature size of transistors, the large number of devices within one circuit, and the high operating frequency, the effect of these variations on the performance of 3-D ICs becomes increasingly significant. Accurately and efficiently estimating and controlling these variations are, consequently, critical tasks for the design of 3-D ICs