Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm

A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 [email protected] V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

A Low-Power, Reconfigurable, Pipelined ADC with Automatic Adaptation for Implantable Bioimpedance Applications

Biomedical monitoring systems that observe various physiological parameters or electrochemical reactions typically cannot expect signals with fixed amplitude or frequency as signal properties can vary greatly even among similar biosignals. Furthermore, advancements in biomedical research have resulted in more elaborate biosignal monitoring schemes which allow the continuous acquisition of important patient information. Conventional ADCs with a fixed resolution and sampling rate are not able to adapt to signals with a wide range of variation. As a result, reconfigurable analog-to-digital converters (ADC) have become increasingly more attractive for implantable biosensor systems. These converters are able to change their operable resolution, sampling rate, or both in order convert changing signals with increased power efficiency. Traditionally, biomedical sensing applications were limited to low frequencies. Therefore, much of the research on ADCs for biomedical applications focused on minimizing power consumption with smaller bias currents resulting in low sampling rates. However, recently bioimpedance monitoring has become more popular because of its healthcare possibilities. Bioimpedance monitoring involves injecting an AC current into a biosample and measuring the corresponding voltage drop. The frequency of the injected current greatly affects the amplitude and phase of the voltage drop as biological tissue is comprised of resistive and capacitive elements. For this reason, a full spectrum of measurements from 100 Hz to 10-100 MHz is required to gain a full understanding of the impedance. For this type of implantable biomedical application, the typical low power, low sampling rate analog-to-digital converter is insufficient. A different optimization of power and performance must be achieved. Since SAR ADC power consumption scales heavily with sampling rate, the converters that sample fast enough to be attractive for bioimpedance monitoring do not have a figure-of-merit that is comparable to the slower converters. Therefore, an auto-adapting, reconfigurable pipelined analog-to-digital converter is proposed. The converter can operate with either 8 or 10 bits of resolution and with a sampling rate of 0.1 or 20 MS/s. Additionally, the resolution and sampling rate are automatically determined by the converter itself based on the input signal. This way, power efficiency is increased for input signals of varying frequency and amplitude

Sampled charge reuse for power reduction in switched capacitor data converters

Advances in semiconductor fabrication have enabled the shrinking of digital systems dramatically over the years. Although digital circuitry benefits tremendously from the constant shrinking of the device sizes, the benefits for analog circuits are not quite so dramatic. Low power is of critical importance in all mobile devices. Any reduction in power in the embedded analog-to-digital converters (ADCs) in such devices can help prolong the battery life. A technique is proposed that can be used to reduce power dissipation in ADCs that use switched-capacitor gain stages. It is shown for a pipeline ADC that the signal charge stored across the feedback capacitor from the first stage can be reused in the second stage at the end of the first stage\u27s amplify phase. The extra overhead of an extra capacitor is justified by the power savings of the proposed scheme;A well known approach for reducing the power dissipation in pipelined ADCs is the scaling down of capacitors progressively down the pipeline stream. The proposed technique combines the scaling of the capacitors with charge reuse. This combination inherits the power saving benefits of capacitor scaling and adds to the power saving by sharing the capacitor in two consecutive stages. Due to the highest power budget allocated to the first two stages, the sharing 2 is limited to the first two stages. Additionally, it is shown that the charge reuse results in reducing the total capacitive load driven by a stage\u27s opamp, potentially reducing the current requirements of the opamp;The proposed technique has been adapted for use in cyclic ADCs. The proposed technique reuses the charge from the first cycle in the next. This approach helps to reduce the die area of the capacitors in the switched capacitor network by up to 50%. Consequently, the power consumption requirement of the operational amplifier can be reduced. This is achieved while maintaining the thermal noise performance and conversion rate of the conventional structure. A 10-bit, 2.3MHz cyclic ADC using the new structure is implemented in 0.5mum CMOS. Spectre simulation results show a THD of -76dB and SFDR of -74.95dB

Pipelined analog-to-digital conversion using current-mode reference shifting

Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica e de ComputadoresPipeline Analog-to-digital converters (ADCs) are the most popular architecture for high-speed medium-to-high resolution applications. A fundamental, but often unreferenced building block of pipeline ADCs are the reference voltage circuits. They are required to maintain a stable reference with low output impedance to drive large internal switched capacitor loads quickly. Achieving this usually leads to a scheme that consumes a large portion of the overall power and area. A review of the literature shows that the required stable reference can be achieved with either on-chip buffering or with large off-chip decoupling capacitors. On-chip buffering is ideal for system integration but requires a high speed buffer with high power dissipation. The use of a reference with off-chip decoupling results in significant power savings but increases the pads of chip, the count of external components and the overall system cost. Moreover the amount of ringing on the internal reference voltage caused by the series inductance of the package makes this solution not viable for high speed ADCs. To address this challenge, a pipeline ADC employing a multiplying digital-to-analog converter (MDAC) with current-mode reference shifting is presented. Consequently, no reference voltages and, therefore, no voltage buffers are necessary. The bias currents are generated on-chip by a reference current generator that dissipates low power. The proposed ADC is designed in a 65 nm CMOS technology and operates at sampling rates ranging from 10 to 80 MS/s. At 40 MS/s the ADC dissipates 10.8 mW from a 1.2 V power supply and achieves an SNDR of 57.2 dB and a THD of -68 dB, corresponding to an ENOB of 9.2 bit. The corresponding figure of merit is 460 fJ/step

Design of Low Power and Power Scalable Pipelined ADC Using Current Modulated Power Scale

This work represents a power scalable pipelined ADC, which achieves low power variation depends upon the sampling rate and enables variation in throughput. The keys to power scalability at high sampling rates were current modulation-based architecture and the development of novel rapid power-on Op-amp, which can completely and quickly power on/off by the feedback approach. The result achieved in this design is as high as 50 Msps and as low as 1 ksps, keeping some important parameters of ADC as ENOB and SNDR are almost constant. Power variation in ADC has a flexible range from 7.5 µW to 17 mW, which is lower power consumption than previous works

Low power data converters for specific applications

Due to increasing importance of portable equipment and reduction of the supply voltage due to technology scaling, recent efforts in the design of mixed-signal circuits have focused on developing new techniques to reduce the power dissipation and supply voltage. This requires research into new architectures and circuit techniques that enable both integration and programmability. Programmability allows each component to be used for different applications, reducing the total number of components, and increased integration by eliminating external components will reduce cost and power;Since data converters are used in many different applications, in this thesis new low voltage and low power data converter techniques at both the architecture and circuit design levels are investigated to minimize power dissipation and supply voltage. To demonstrate the proposed techniques, test the performance of the proposed architectures, and verify their effectiveness in terms of power savings, five prototype chips are fabricated and tested;First, a re-configurable data converter (RDC) architecture is presented that can be programmed as analog-to-digital converter (ADC), digital-to-analog converter (DAC), or both. The reconfigurability of the RDC to different numbers of ADCs and DACs having different speeds and resolutions makes it an ideal choice for analog test bus, mixed-mode boundary scan, and built-in self test applications. It combines the advantages of both analog test buses and boundary scan techniques while the area overhead of the proposed techniques is very low compared to the mixed-mode boundary scan techniques. RDC can save power by allowing the designer to program it as the right converter for desired application. This architecture can be potentially implemented inside a field programmable gate array (FPGA) to allow the FPGA communicate with the analog world. It can also be used as a stand-alone product to give flexibility to the user to choose ADC/DAC combinations for the desired application;Next, a new method for designing low power and small area ROMless direct digital frequency synthesizers (DDFSs) is presented. In this method, a non-linear digital-to-analog converter is used to replace the phase-to-sine amplitude ROM look-up table and the linear DAC in conventional DDFS. Since the non-linear DAC converts the phase information directly into analog sine wave, no phase-to-amplitude ROM look-up table is required;Finally, a new low voltage technique based on biased inverting opamp that can have almost rail-to-rail swing with continuously valid output is discussed. Based on this biasing technique, a 10-bit segmented R-2R DAC and an 8-bit successive approximation ADC are designed and presented

Low power VCO-based analog-to-digital conversion

textThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Electrical and Computer Engineerin