STUDY OF FULLY-INTEGRATED LOW-DROPOUT REGULATORS

Department of Electrical EngineeringThis thesis focuses on the introduction of fully-integrated low-dropout regulators (LDOs). Recently, for the mobile and internet-of-things applications, the level of integration is getting higher. LDOs get popular in integrated circuit design including functions such as reducing switching ripples from high-efficiency regulators, cancelling spurs from other loads, and giving different supply voltages to loads. In accordance with load applications, choosing proper LDOs is important. LDOs can be classified by the types of power MOSEFT, the topologies of error amplifier, and the locations of dominant pole. Analog loads such as voltage-controlled oscillators and analog-to-digital converters need LDOs that have high power-supply-rejection-ratio (PSRR), high accuracy, and low noise. Digital loads such as DRAM and CPU need fast transient response, a wide range of load current providable LDOs. As an example, we present the design procedure of a fully-integrated LDO that obtains the desired PSRR. In analog LDOs, we discuss advanced techniques such as local positive feedback loop and zero path that can improve stability and PSRR performance. In digital LDOs, the techniques to improve transient response are introduced. In analog-digital hybrid LDOs, to achieve both fast transient and high PSRR performance in a fully-integrated chip, how to optimally combine analog and digital LDOs is considered based on the characteristics of each LDO type. The future work is extracted from the considerations and limitations of conventional techniques.clos

Supercapacitor assisted low dropout regulators (SCALDO) with reduced switches: A new approach to high efficiency VRM designs

Supercapacitor assisted low dropout (SCALDO) regulator is a new approach to develop high efficiency DC-DC converters with supercapacitors used for energy recovery. One limitation in these topologies is that in some configurations a large number of low-speed switches are required. If the SCALDO technique is adapted to build voltage regulator modules (VRM), it is necessary to reduce number of switches combined with a high current capable LDO. A new topology-variation with less number of switches can be achieved by reconfiguring the original SCALDO and adding an extra LDO to the circuit. The paper presents a summary of some preliminary work, and experimental results for a 2.5V proof of concept-prototype

Supercapacitor assisted LDO (SCALDO) techniquean extra low frequency design approach to high efficiency DC-DC converters and how it compares with the classical switched capacitor converters

Supercapacitor assisted low dropout regulators (SCALDO) were proposed as an alternative design approach to DC-DC converters, where the supercapacitor circulation frequency (switching frequency) is in the order of few Hz to few 10s of Hz, with an output stage based on a low dropout regulator stage. For converters such as 12–5V, 5–3.3V and 5–1.5V, the technique provides efficiency improvement factors of 2, 1.33 and 3 respectively, in compared to linear converters with same input-output combinations. In a 5–1.5V SCALDO regulator, using thin profile supercapacitors in the range of fractional farads to few farads, this translates to an approximate end to end efficiency of near 90%. However, there were concerns that this patented technique is merely a variation of well-known switched capacitor (charge pump) converters. This paper is aimed at providing a broad overview of the capability of SCALDO technique with generalized theory, indicating its capabilities and limitations, and comparing the practical performance with a typical switched capacitor converter of similar current capability

Development of high-performance low-dropout regulators for SoC applications.

Or, Pui Ying."July 2010."Thesis (M.Phil.)--Chinese University of Hong Kong, 2010.Includes bibliographical references.Abstracts in English and Chinese.AcknowledgmentsTable of ContentList of FiguresList of TablesList of PublicationsChapter Chapter 1 - --- Background of LDO ResearchChapter 1.1 --- Structure of a LDO --- p.1-1Chapter 1.2 --- Principle of Operation of LDO --- p.1-2Chapter 1.3 --- Steady-State Specification of LDO --- p.1-3Chapter 1.4 --- High-Frequency Specification of LDO --- p.1-3Chapter 1.5 --- Dynamic Specification of LDO --- p.1-4Chapter 1.6 --- An Advanced LDO Structure --- p.1-4Chapter 1.7 --- Contribution and Outline of the Thesis --- p.1-5References --- p.1-6Chapter Chapter 2 - --- PSRR AnalysisChapter 2.1 --- Modeling of the PSRR of LDO --- p.2-3Chapter 2.2 --- Analysis of LDO Circuit Using Proposed Modeling --- p.2-6Chapter 2.3 --- Conclusion of Chapter --- p.2-12References --- p.2-13Chapter Chapter 3- --- An Output-Capacitorless LDO with Direct Voltage-Spike DetectionChapter 3.1 --- Analysis of Output-Capacitorless LDO --- p.3-5Chapter 3.2 --- LDO with Proposed Voltage-Spike Detection Circuit --- p.3-7Chapter 3.3 --- Experimental Results --- p.3-15Chapter 3.4 --- Conclusion of Chapter --- p.3-21References --- p.3-22Chapter Chapter 4 - --- A LDO with Impedance Adjustment and Loop-Gain Boosting TechniqueChapter 4.1 --- Proposed LDO --- p.4-3Chapter 4.2 --- Experimental Results --- p.4-7Chapter 4.3 --- Comparison --- p.4-11Chapter 4.4 --- Conclusion of Chapter --- p.4-12Reference --- p.4-13Chapter Chapter 5 - --- Conclusion and Future Wor

Characterization of the FE-I4B pixel readout chip production run for the ATLAS Insertable B-layer upgrade

The Insertable B-layer (IBL) is a fourth pixel layer that will be added inside the existing ATLAS pixel detector during the long LHC shutdown of 2013 and 2014. The new four layer pixel system will ensure excellent tracking, vertexing and b-tagging performance in the high luminosity pile-up conditions projected for the next LHC run. The peak luminosity is expected to reach 3 x 10^34 cm^-2 s^-1 with an integrated luminosity over the IBL lifetime of 300 fb^-1 corresponding to a design lifetime fluence of 5 x 10^15 n_eq cm^-2 and ionizing dose of 250 Mrad including safety factors. The production front-end electronics FE-I4B for the IBL has been fabricated at the end of 2011 and has been extensively characterized on diced ICs as well as at the wafer level. The production tests at the wafer level were performed during 2012. Selected results of the diced IC characterization are presented, including measurements of the on-chip voltage regulators. The IBL powering scheme, which was chosen based on these results, is described. Preliminary wafer to wafer distributions as well as yield calculations are given

A Wireless Implantable System for Facilitating Gastrointestinal Motility.

Gastrointestinal (GI) electrical stimulation has been shown in several studies to be a potential treatment option for GI motility disorders. Despite the promising preliminary research progress, however, its clinical applicability and usability are still unknown and limited due to the lack of a miniaturized versatile implantable stimulator supporting the investigation of effective stimulation patterns for facilitating GI dysmotility. In this paper, we present a wireless implantable GI modulation system to fill this technology gap. The system consists of a wireless extraluminal gastrointestinal modulation device (EGMD) performing GI electrical stimulation, and a rendezvous device (RD) and a custom-made graphical user interface (GUI) outside the body to wirelessly power and configure the EGMD to provide the desired stimuli for modulating GI smooth muscle activities. The system prototype was validated in bench-top and in vivo tests. The GI modulation system demonstrated its potential for facilitating intestinal transit in the preliminary in vivo chronic study using porcine models

Quasi-digital low-dropout voltage regulators uses controlled pass transistors

This article presents a low quiescent current output capacitorless quasi-digital CMOS LDO regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is broken up to two smaller sizes based on a breakup criterion defined here, which considers the maximum output voltage variations to different load current steps to find the suitable current boundary for breaking up. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Therefore, using one smaller transistor for low load currents, and another one larger for higher currents, is the best trade-off between output variations, complexity, and power dissipation. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.35 µm CMOS process to supply a load current between 0-100 mA while consumes 7.6 µA quiescent current. The results reveal 46% and 69% improvement on the output voltage variations and settling time, respectively.Postprint (published version

An 11 mA Capacitor-Less LDO With 3.08 nA Quiescent Current and SSF-Based Adaptive Biasing

This brief presents an ultra-low power low-dropout (LDO) regulator with an experimental total quiescent current consumption of only 3.08 nA. The circuit is designed to operate with a load current in the range 0 - 11 mA. A novel adaptive biasing scheme based on a super source follower (SSF) structure is proposed, which measures the absolute voltage difference between the two inputs of the LDO’s error amplifier and modifies the biasing current accordingly. Thus, the transient response of the regulator is improved by counteracting the effect of using such a low bias current. The proposed LDO has been fabricated in a standard CMOS 180 nm process and the experimental characterization showed an outstanding performance in terms of maximum load current over quiescent current consumption ratio.S