FPGA-based High Performance Diagnostics For Fusion

High performance diagnostics are an important aspect of fusion research. Increasing shot-lengths paired with the requirement for higher accuracy and speed make it mandatory to employ new technology to cope with the increasing demands on digitization and data handling. Field programmable gate arrays (FPGAs) are well known in high performance applications. Their ability to handle multiple fast data streams whilst remaining programmable make them an ideal tool for diagnostic development. Both the improvement of old and the design of new diagnostics can benefit from FPGA-technology and increase the amount of accessible physics significantly. In this work the developments on two FPGA-based diagnostics are presented. In the first part a new open-hardware low-cost FPGA-based digitizer is presented for the MAST-Upgrade (MAST-U) integral electron density interferometer. The system is shown to have an optically limited phase accuracy and a detection bandwidth of over 3.5 MHz. Data is acquired continuously at 20 MS/s and streamed to an acquisition PC via optical fiber. By employing a dual-FPGA approach real-time processing of the density signal can be achieved despite severly limited resources, thus providing a control signal for the MAST-U plasma control system system with less than 8 μs latency. Due to MAST-U being still inoperable, in-situ testing has been conducted on the ASDEX Upgrade, where fast wave physics up to 3.5 MHz could first be observed. The second part presents developments to the Synthetic Aperture Microwave Imaging (SAMI) diagnostic. In addition to improving the utilization of long shot-lengths and enabling dual-polarized acquisition the system has been enhanced to continuously acquire active probing profiles for 2D Doppler back-scattering (DBS), a technique recently developed using SAMI. The aim is to measure pitch angle profiles to derive the edge current density. SAMI has been transferred to the NSTX-Upgrade and integrated into the experiment’s infrastructure, where it has been acquiring data since May 2016. As part of this move an investigation into near-field effects on SAMI’s image reconstruction algorithms was conducted

Advancements in Multinuclear Multichannel NMR and MRI

The introduction of receive arrays revolutionized ^1H MRI and in vivo NMR by increasing SNR and enabling accelerated imaging. All MRI scanners manufactured today are equipped to receive signals from ^1H array coils, but few support multi-channel reception for other nuclei. The extension of receive arrays to non^1H nuclei has proven difficult because of the lack of broadband array receivers. These nuclei often have low sensitivity and stand to benefit greatly from the increase in SNR arrays provide. This dissertation presents a variety of technologies that have been developed to enable the development and use of X-nuclear and multi-nuclear arrays. Frequency conversion receiver front-ends provide a straightforward and cost-effective approach for adapting standard ^1H multi-channel array receivers for use with other nuclei. Two generations of frequency translation receiver front-ends have been developed that use active mixers to convert the received signal from a non^1H array to the ^1H frequency for reception by the host system receiver. This first-generation system has been demonstrated on 4.7T and 7T systems without any decrease in SNR as compared to the stock systems, and has been shown to be capable of accommodating ^1H decoupling. The second-generation receiver was developed to add the capability to simultaneously convert signals received from multiple nuclei as well as to streamline the setup and use of the translation system. Frequency translation has been shown to be able to convert ^1H-only multi-channel receivers for use with other nuclei with minimal degradation of SNR. In addition, a standalone broadband system capable of simultaneous multi-nuclear imaging and spectroscopy at 1T and 4.7T has been developed. This system can either operate completely independently or interface with existing systems. The broadband system has been demonstrated with simultaneous imaging and spectroscopy of three nuclei. This work allows existing multi-channel MRI receivers to be adapted to receive signals from nuclei other than hydrogen, allowing for the use of receive arrays for in vivo multi-nuclear NMR

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

Digital radar receiver design based on highly efficient bandpass sampling FPGA architecture

Thesis (M.S.)--University of Oklahoma, 2009.Includes bibliographical references (leaves 62-64).As digital electronics become faster and more efficient, it becomes possible to move the analog/digital interface in a radar downconversion system further towards the antenna. Instead of digitizing radar echoes at the end of the down-conversion process, digital logic can perform the same operations previously performed by analog components. Taking full advantage of this opportunity will result in a more highly integrated and reconfigurable design. By removing unnecessary analog components, the error from component variability and noise injected into the signal of interest is reduced, the size of the receiver and the power required for operation is minimized, and the overall cost of the system can be lowered. This research is focused on employing software defined radio concepts for weather observation, thus creating a low-cost digital radar receiver at the University of Oklahoma for use in radar projects as a way of obviating the need for commmercial radar receivers, which can be many times more expensive. Software-defined radio techniques, such as bandpass sampling, are used to achieve a high data processing bandwidth and oversampling ratio with the smallest logic resource utilization. Two novel digital receiver designs are discussed in this thesis. A prototype compact single-channel digital receiver based on a 14-bit analog-to-digital converter and a hand-solderable Xilinx FPGA was built and tested both in the laboratory and at the National Weather Radar Testbed (NWRT). Building on the lessons learned from testing the single-channel digital radar receiver, a second digital receiver was designed for expanded capabilities. Through the utilization of a low-power, simultaneous-sampling eight channel ADC with high-speed serial data links and a cost-efficient FPGA with integrated DSP slices, eight data channels can be digitized, processed and transferred at the same time in a compact form factor. An ethernet interface has been included which allows for a scalable control channel so that the digital receiver's operations can be quickly modified. This also makes it possible to remotely change the firmware of the FPGA in seconds, without the need for physical access. Development of host computer platforms to store and process each digital receiver's output are also discussed

Subsampling receivers with applications to software defined radio systems

Este trabajo de tesis propone la utilización sistemas basados en submuestreo como una alternativa para la implementación de la etapa de down-conversion de los receptores de radio frecuencia (RF) empleados para aplicaciones multi-estándar y SDR (Software Defined Radio). El objetivo principal será el de optimizar el diseño en cuanto a flexibilidad y simplicidad, las cuales son propiedades inherentes en los sistemas basados en submuestreo. Por tanto, como reducir el número de componentes al mínimo es clave cuando un mismo receptor procesa diferentes estándares de comunicación, las arquitecturas basadas en submuestreo han sido seleccionadas, donde la reusabilidad de los componentes empleados es posible, así como la reducción de los costes totales de los receptores de comunicación y de los equipos de certificación que emplean estas arquitecturas. Un motivo adicional por el que los sistemas basados en submuestreo han sido seleccionados es el concerniente a la topología del receptor. Como la idea de la tecnología SDR es implementar todas las funcionalidades del receptor (filtrado, amplificación) en el dominio digital, el convertidores analógico-digital (ADC) deberá estar localizado en la cadena de recepción lo más cerca posible a la antena, siendo el objetivo final el convertir la señal directamente de RF a digital. Sin embargo, con los actuales ADC no es posible implementar esta idea debido al alto ancho de banda que necesitarían sin perder resolución para cubrir las especificaciones de los estándares de comunicaciones inalámbricas. Por tanto, los sistemas basados en submuestreo se presentan como la opción más adecuada para implementar este tipo de sistemas debido a que pueden muestrear la señal de entrada por debajo de la tasa de Nyquist, si se cumplen ciertas restricciones en cuanto a la elección de la frecuencia de muestreo. De este modo, los requerimientos del ADC serán relajados ya que, usando estas arquitecturas, este componente procesará la señal a frecuencias intermedias. Una vez se han introducido los conceptos principales de las técnicas de submuestreo, esta tesis doctoral presenta el diseño de una tarjeta de adquisición de datos basada en submuestreo con la finalidad de ser implementada como un receptor de test y certificación de banda ancha. El sistema propuesto proporciona una alta resolución para un elevado ancho de banda, a partir del uso de un S&H de bajo jitter y de un convertidor analógico digital ADC que trabaja a frecuencias intermedias. El sistema es implementado usando dispositivos comerciales en una placa de circuito impreso diseñada y fabricada, y cuya caracterización experimental muestra una resolución de más 8 bits para un ancho de banda analógico de 20 MHz. Concretamente, la resolución medida será mayor de 9 bits hasta una frecuencia de entrada de 2.9 GHz y mayor de 8 bits para una frecuencia de entrada de hasta 6.5 GHz, lo cual resulta suficiente para cubrir los requerimientos de la mayor parte de los actuales estándares de comunicaciones inalámbricas (GPS, GSM, GPRS, UMTS, Bluetooth, Wi-Fi, WiMAX). Sin embargo, los receptores basados en submuestreo presentan algunos importantes inconvenientes, como son adicionales fuentes de ruido (jitter y plegado de ruido térmico) y una dificultad añadida para implementarlo en escenarios multi-banda y no lineales. Acerca del plegado de ruido en la banda de interés, esta tesis propone el uso de una técnica basada en una arquitectura de reloj múltiple con el objetivo de aumentar la resolución y cubrir un número mayor de estándares para su test y certificación. Empleando una frecuencia de muestreo mayor para el caso del S&H, se conseguirá reducir este efecto, aumentando la resolución en aproximadamente 0.5-1 bit respecto al caso de sólo usar una fuente de reloj. Las expresiones teóricas de esta mejora son desarrolladas y presentadas en esta tesis, siendo posteriormente corroboradas de modo experimental. Por otra parte, esta tesis también propone novedosas técnicas para la aplicación de estos sistemas de submuestreo en entornos multi-banda y no lineales, los cuales presentan desafíos adicionales por el hecho de existir la posibilidad de solapamiento entre la señal de interés y los otros canales de comunicación, así como de solapamiento con sus armónicos. De este modo, esta tesis extiende el uso de los sistemas basados en submuestreo para este tipo de entornos, proponiendo técnicas para la elección de la frecuencia óptima de muestreo que evitan el solapamiento entre señales, a la vez que consiguen incrementar la resolución del receptor. Finalmente, se presentará la optimización en cuanto a características de ruido de un receptor concreto para aplicaciones de banda dual en entornos no lineales. Dicho receptor estará basado en las técnicas de reloj múltiple presentadas anteriormente y en una estructura de multi-filtro entre el S&H y el ADC. El sistema diseñado podrá emplearse para diversas aplicaciones a ambos lados de la cadena de comunicación, tal como en receptores de detección de espectro para radio cognitiva, o implementando el bucle de realimentación de un transmisor para la linealización de amplificadores de potencia. Por tanto, la presente tesis doctoral cuenta con tres contribuciones diferenciadas. La primera de ellas es la dedicada al diseño de un prototipo de recepción multi-estándar basado en submuestreo para aplicaciones de test y certificación. La segunda aportación es la dedicada a la optimización de las especificaciones de ruido a partir de las técnicas presentadas basadas en reloj múltiple. Por último, la tercera contribución principal es la relacionada con la extensión de este tipo de técnicas a sistemas multi-banda en entornos no lineales. Todas estas contribuciones han sido estudiadas teóricamente y experimentalmente validadas

RHINO software-defined radio processing blocks

This MSc project focuses on the design and implementation of a library of parameterizable, modular and reusable Digital IP blocks designed around use in Software-Defined Radio (SDR) applications and compatibility with the RHINO platform. The RHINO platform has commonalities with the better known ROACH platform, but it is a significantly cut-down and lowercost alternative which has similarities in the interfacing and FPGA/Processor interconnects of ROACH. The purpose of the library and design framework presented in this work aims to alleviate some of the commercial, high cost and static structure concerns about IP cores provided by FPGA manufactures and third-party IP vendors. It will also work around the lack of parameters and bus compatibility issues often encountered when using the freely available open resources. The RHINO hardware platform will be used for running practical applications and testing of the blocks. The HDL library that is being constructed is targeted towards both novice and experienced low-level HDL developers who can download and use it for free, and it will provide them experience of using IP Cores that support open bus interfaces in order to exploit SoC design without commercial, parameter and bus compatibility limitations. The provided modules will be of particularly benefit to the novice developers in providing ready-made examples of processing blocks, as well as parameterization settings for the interfacing blocks and associated RF receiver side configuration settings; all together these examples will help new developers establish effective ways to build their own SDR prototypes using RHINO

A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009

Compressive Sensing of Multiband Spectrum towards Real-World Wideband Applications.

PhD Theses.Spectrum scarcity is a major challenge in wireless communication systems with their rapid evolutions towards more capacity and bandwidth. The fact that the real-world spectrum, as a nite resource, is sparsely utilized in certain bands spurs the proposal of spectrum sharing. In wideband scenarios, accurate real-time spectrum sensing, as an enabler of spectrum sharing, can become ine cient as it naturally requires the sampling rate of the analog-to-digital conversion to exceed the Nyquist rate, which is resourcecostly and energy-consuming. Compressive sensing techniques have been applied in wideband spectrum sensing to achieve sub-Nyquist-rate sampling of frequency sparse signals to alleviate such burdens. A major challenge of compressive spectrum sensing (CSS) is the complexity of the sparse recovery algorithm. Greedy algorithms achieve sparse recovery with low complexity but the required prior knowledge of the signal sparsity. A practical spectrum sparsity estimation scheme is proposed. Furthermore, the dimension of the sparse recovery problem is proposed to be reduced, which further reduces the complexity and achieves signal denoising that promotes recovery delity. The robust detection of incumbent radio is also a fundamental problem of CSS. To address the energy detection problem in CSS, the spectrum statistics of the recovered signals are investigated and a practical threshold adaption scheme for energy detection is proposed. Moreover, it is of particular interest to seek the challenges and opportunities to implement real-world CSS for systems with large bandwidth. Initial research on the practical issues towards the real-world realization of wideband CSS system based on the multicoset sampler architecture is presented. In all, this thesis provides insights into two critical challenges - low-complexity sparse recovery and robust energy detection - in the general CSS context, while also looks into some particular issues towards the real-world CSS implementation based on the i multicoset sampler

Topical Workshop on Electronics for Particle Physics

The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities