DESIGN OF AN ENERGY-EFFICIENT CONSTANT DELAY LOGIC FOR LOW POWER APPLICATIONS

An Energy Efficient Constant Delay Logic (EE-CDL) is proposed in this thesis to reduce the power consumption for low power applications. The EE-CDL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. It has a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage are ready. The proposed logic style requires low power when compared to the existing CDL. The proposed circuit is designed and using 90-nm, CMOS technology file with supply voltage 1.2V. An inverter is designed using energy efficient feedthrough logic and simulated in MicroWind. The simulation result shows that the proposed logic reduces the power consumption by 88%, 83% and 56% when compared with FTL, Low Power FTL (LP-FTL) and Constant Delay Logic (CDL) respectively. The problem of requirement of inverter as in dynamic logic is completely eliminated in the proposed logic

Expansion of CMOS array design techniques

The important features of the multiport (double entry) automatic placement and routing programs for standard cells are described. Measured performance and predicted performance were compared for seven CMOS/SOS array types and hybrids designed with the high speed CMOS/SOS cell family. The CMOS/SOS standard cell data sheets are listed and described

High Performance Logic for Arithmetic Circuits

The objective of this project is to design high performance arithmetic circuits which are faster and have lower power consumption using a new dynamic logic family of CMOS and to analyze its performance for sequential circuits and effects upon cascading. This new dynamic logic family is known as Feedthrough logic. It has two basic structures: high speed (HS0) and low power (LP0). It allows for commencement of evaluation in a computational block before its evaluation phase begins, and quickly performs a final evaluation as soon as the inputs are valid. This dynamic logic family is best suited to arithmetic circuits because the critical path is made of a long chain of cascaded inverting gates. As the major advantage of this logic which is higher speed is observed upon cascading, it’s most suitable for arithmetic circuits. We compare a set of ripple carry adders 4 bit and 16 bit in domino logic with the two basic structures derived. Experimental results have shown that the lower power structure provides for smaller power delay product when compared with domino logic. Certain modifications in the logic style are proposed to optimize the performance when applied to a single ended or double ended flip flops. The effects upon cascading are analyzed by using a 4-bit register. As delay is not propagated in a register circuit or any other synchronous sequential circuit (the circuit being edge triggered), the major advantage of this logic which is observed upon cascading cannot possibly be observed for sequential circuits. So even though the circuit can be optimised by feedthrough logic, this logic is not preferred for sequential circuits. So finally we have carried out the tapeout of 16 bit adder in LP0 using 180 UMC CMOS process flow

Analysis and application of improved feedthrough logic

Continuous technology scaling and increased frequency of operation of VLSI circuits leads to increase in power density which raises thermal management problem. Therefore design of low power VLSI circuit technique is a challenging task without sacrificing its performance. This thesis presents the design of a low power dynamic circuit using a new CMOS domino logic family called feedthrough (FTL) logic. Dynamic logic circuits are more significant because of its faster speed and lesser transistor requirement as compared to static CMOS logic circuits. The need for faster circuits compels designers to use FTL as compared static and domino CMOS logic and the requirement of output inverter for cascading of various logic blocks in domino logic are eliminated in the proposed design. The proposed circuit for low power (LP-FTL) improves dynamic power consumption as compared to the existing FTL and to further improve its speed we propose another circuit (HS-FTL). This logic family improves speed at the cost of dynamic power consumption and area. Proposed modified FTL circuit families provide better PDP as compared to the existing FTL. Simulation results of both the proposed circuit using 0.18 µm, 1.8 V CMOS process technology indicate that the LP-FTL structure reduces the dynamic power approximately by 42% and the HS-FTL structure achieves a speed up- 1.4 for 10-stage of inverters and 8-bit ripple carry adder in comparison to existing FTL logic. Furthermore, we present various circuit design techniques to improve noise tolerance of the proposed FTL logic families. Noise in deep submicron technology limits the reliability and performance of ICs. The ANTE (average noise threshold energy) metric is used for the analysis of noise tolerance of proposed FTL. A 2-input NAND and NOR gate is designed by the proposed technique. Simulation results for a 2-input NAND gate at 0.18-µm, 1.8 V CMOS process technology show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction in leakage power. Continuous scaling of technology towards the nanometer range significantly increases leakage current level and the effect of noise. This research can be further extended for performance optimization in terms of power, speed, area and noise immunity

A Constant Delay Logic Style - An Alternative Way of Logic Design

High performance, energy efficient logic style has always been a popular research topic in the field of very large scale integrated (VLSI) circuits because of the continuous demands of ever increasing circuit operating frequency. The invention of the dynamic logic in the 80s is one of the answers to this request as it allows designers to implement high performance circuit block, i.e., arithmetic logic unit (ALU), at an operating frequency that traditional static and pass transistor CMOS logic styles are difficult to achieve. However, the performance enhancement comes with several costs, including reduced noise margin,charge-sharing noise, and higher power dissipation due to higher data activity. Furthermore, dynamic logic has gradually lost its performance advantage over static logic due to the increased self-loading ratio in deep-submicron technology (65nm and below) because of the additional NMOS CLK footer transistor. Because of dynamic logic's limitations and diminished speed reward, a slowly rising need has emerged in the past decade to explore new logic style that goes beyond dynamic logic. In this thesis a constant delay (CD) logic style is proposed. The constant delay characteristic of this logic style regardless of the logic expression makes it suitable in implementing complicated logic expression such as addition. Moreover, CD logic exhibits a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage is ready. This feature enables performance advantage over static and dynamic logic styles in a single cycle, multi-stage circuit block. Several design considerations including appropriate timing window width adjustment to reduce power consumption and maintain sufficient noise margin to ensure robust operations are discussed and analyzed. Using 65nm general purpose CMOS technology, the proposed logic demonstrates an average speed up of 94% and 56% over static and dynamic logic respectively in five different logic expressions. Post layout simulation results of 8-bit ripple carry adders conclude that CD-based design is 39% and 23% faster than the static and dynamic-based adders respectively. For ultra-high speed applications, CD-based design exhibits improved energy, power-delay product, and energy-delay product efficiency compared to static and dynamic counterparts

High-Performance, Energy-Efficient CMOS Arithmetic Circuits

In a modern microprocessor, datapath/arithmetic circuits have always been an important building block in delivering high-performance, energy-efficient computing, because arithmetic operations such as addition and binary number comparison are two of the most commonly used computing instructions. Besides the manufacturing CMOS process, the two most critical design considerations for arithmetic circuits are the logic style and micro-architecture. In this thesis, a constant-delay (CD) logic style is proposed targeting full-custom high-speed applications. The constant delay characteristic of this logic style (regardless of the logic type) makes it suitable for implementing complicated logic expressions such as addition. CD logic exhibits a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage are ready. This feature enables a performance advantage over static and dynamic domino logic styles in a single cycle, multi-stage circuit block. Several design considerations including timing window width adjustment and clock distribution are discussed. Using a 65-nm general-purpose CMOS technology, the proposed logic style demonstrates an average speedup of 94% and 56% over static and dynamic domino logic, respectively, in five different logic gates. Simulation results of 8-bit ripple carry adders conclude that CD logic is 39% and 23% faster than the static and dynamic-based adders, respectively. CD logic also demonstrates 39% speedup and 64% (22%) energy-delay product reduction from static logic at 100% (10%) data activity in 32-bit carry lookahead adders. To confirm CD logic's potential, a 148 ps, single-cycle 64-bit adder with CD logic implemented in the critical path is fabricated in a 65-nm, 1-V CMOS process. A new 64-bit Ling adder micro-architecture, which utilizes both inversion and absorption properties to minimize the number of CD logic and the number of logic stage in the critical path, is also proposed. At 1-V supply, this adder's measured worst-case power and leakage power are 135 mW and 0.22 mW, respectively. A single-cycle 64-bit binary comparator utilizing a radix-2 tree structure is also proposed. This comparator architecture is specifically designed for static logic to achieve both low-power and high-performance operation, especially in low input data activity environments. At 65-nm technology with 25% (10%) data activity, the proposed design demonstrates 2.3x (3.5x) and 3.7x (5.8x) power and energy-delay product efficiency, respectively. This comparator is also 2.7x faster at iso-energy (80 fJ) or 3.3x more energy-efficient at iso-delay (200 ps) than existing designs. An improved comparator, where CD logic is utilized in the critical path to achieve high performance without sacrificing the overall energy efficiency, is also realized in a 65-nm 1-V CMOS process. At 1-V supply, the proposed comparator's measured delay is 167 ps, and has an average power and a leakage power of 2.34 mW and 0.06 mW, respectively. At 0.3-pJ iso-energy or 250-ps iso-delay budget, the proposed comparator with CD logic is 20% faster or 17% more energy-efficient compared to a comparator implemented with just the static logic

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2

Design and Analysis of Improved Domino Logic with Noise Tolerance and High Performance

The demands of upcoming computing, as well as the challenges of nanometer-era of VLSI design necessitate new digital logic techniques and styles that are at the same time high performance, energy efficient and robust to noise and variation. Dynamic CMOS logic gates are broadly used to design high performance circuits due to their high speed. Conversely, the vital demerit of dynamic logic style is its high noise sensitivity. The main reason for this is the sub-threshold leakage current flowing through the pull down network. With continuous technology scaling, this problem is getting more and more severe. In this thesis, a new noise tolerant dynamic CMOS circuit technique is proposed. In the proposed work, we have enhanced the behavior of the domino CMOS logic. This technique also gets benefit in terms of delay and power. This thesis describes the new low power, noise tolerant and high speed domino logic technique and presents a comparison result of this logic with previously reported schemes. Simulation results prove that, in 180 nm CMOS technology when we used this logic style to realize wide fan-in logic gates, it could achieve maximum level of noise robustness as compared to its basic counterpart. In addition, the logic also works efficiently with sequential circuits. The feasibility of this new technique is demonstrated by means of a real hardware, we have built a custom test-chip in the UMC 180 nm process technology with an ALU core, using the proposed domino logic style for each design block. In this thesis, we have also described the design and implementation of this chip. In addition to this, we have also presented initial power and delay performance comparisons between the circuit level simulated ALU and test-chip implemented in the proposed domino logic style. Finally we conclude that, the thesis contributes a very efficient logic style for wide fan-in gates, which is not only noise robust but also energy efficient and high speed

Palmo : a novel pulsed based signal processing technique for programmable mixed-signal VLSI

In this thesis a new signal processing technique is presented. This technique exploits the use of pulses as the signalling mechanism. This Palmo 1 signalling method applied to signal processing is novel, combining the advantages of both digital and analogue techniques. Pulsed signals are robust, inherently low-power, easily regenerated, and easily distributed across and between chips. The Palmo cells used to perform analogue operations on the pulsed signals are compact, fast, simple and programmable

FEEDFORWARD ARTIFICIAL NEURAL NETWORK DESIGN UTILISING SUBTHRESHOLD MODE CMOS DEVICES

This thesis reviews various previously reported techniques for simulating artificial neural networks and investigates the design of fully-connected feedforward networks based on MOS transistors operating in the subthreshold mode of conduction as they are suitable for performing compact, low power, implantable pattern recognition systems. The principal objective is to demonstrate that the transfer characteristic of the devices can be fully exploited to design basic processing modules which overcome the linearity range, weight resolution, processing speed, noise and mismatch of components problems associated with weak inversion conduction, and so be used to implement networks which can be trained to perform practical tasks. A new four-quadrant analogue multiplier, one of the most important cells in the design of artificial neural networks, is developed. Analytical as well as simulation results suggest that the new scheme can efficiently be used to emulate both the synaptic and thresholding functions. To complement this thresholding-synapse, a novel current-to-voltage converter is also introduced. The characteristics of the well known sample-and-hold circuit as a weight memory scheme are analytically derived and simulation results suggest that a dummy compensated technique is required to obtain the required minimum of 8 bits weight resolution. Performance of the combined load and thresholding-synapse arrangement as well as an on-chip update/refresh mechanism are analytically evaluated and simulation studies on the Exclusive OR network as a benchmark problem are provided and indicate a useful level of functionality. Experimental results on the Exclusive OR network and a 'QRS' complex detector based on a 10:6:3 multilayer perceptron are also presented and demonstrate the potential of the proposed design techniques in emulating feedforward neural networks