Low Cost FPGA Implementation of a SPI over High Speed Optical SerDes

Serial Peripheral Interface (SPI) is a commonly used communication protocol that allows serial data transfer between a master and a slave device over a short distance. However, if we require just SPI over long distances currently there is no effective low-cost solution. A SerDes provides a solution to this shortcoming by sending parallel data as a serial transmission and converting it back at the receiver end. However, most of the current SerDes implementations are expensive to implement and cater to very high-speed applications, which is not the case in SPI. In this paper, we present a simple to implement and low cost SerDes solution for sending and receiving multiple SPI and GPIO lines. Our proposed solution makes use of a low cost CLPD / FPGA and is applicable for low data rate applications such as SPI. This paper investigates the simplest solution to the problem, whilst maintaining a reliable single wire / optical link. For testing, we have implemented three novel encoding schemes that all provided good results, each measured by performance against resource usage. One of these encoding schemes has shown a drop-out rate as low as 0.001% over a 24-hour period. Our proposed solution when used in conjunction with an optical fibre medium could potentially allow SPI transmission over several kilometres of distance

SatCat5: A Low-Power, Mixed-Media Ethernet Network for Smallsats

In any satellite, internal bus and payload systems must exchange a variety of command, control, telemetry, and mission-data. In too many cases, the resulting network is an ad-hoc proliferation of complex, dissimilar protocols with incomplete system-to-system connectivity. While standards like CAN, MIL-STD-1553, and SpaceWire mitigate this problem, none can simultaneously solve the need for high throughput and low power consumption. We present a new solution that uses Ethernet framing and addressing to unify a mixed-media network. Low-speed nodes (0.1-10 Mbps) use simple interfaces such as SPI and UART to communicate with extremely low power and minimal complexity. High-speed nodes use so-called “media-independent” interfaces such as RMII, RGMII, and SGMII to communicate at rates up to 1000 Mbps and enable connection to traditional COTS network equipment. All are interconnected into a single smallsat-area-network using a Layer-2 network switch, with mixed-media support for all these interfaces on a single network. The result is fast, easy, and flexible communication between any two subsystems. SatCat5 is presented as a free and open-source reference implementation of this mixed-media network switch, with power consumption of 0.2-0.7W depending on network activity. Further discussion includes example protocols that can be used on such networks, leveraging IPv4 when suitable but also enabling full-featured communication without the need for a complex protocol stack

Highly Efficient Multi-Gigabit Commandstatus Packet Tunneling Technique In Inter-Fpga Packet Streaming Architecture

High speed serial protocols build upon multi-gigabit transceivers in the FPGA are the backbone of data communication industries. These protocols are now a fundamental requirement for today’s applications as well as addressing the needs of next generation systems. However, transferring command and status packets explicitly in inter-FPGA control links efficiently via multi-gigabit transceivers without wasting data bandwidth become a challenge when architecting a modern design. Though time-division-multiplexing techniques could be deployed to address this issue, dedicated but unused time-slots for control link packets adversely affect the bandwidth efficiency and thus the system performance. Another common solution focuses on transferring the command and status packets in a separate control link; typically implemented in low to medium bandwidth serial protocols such as I2C and SPI. Though this solution is simple to implement in hardware with readily available device drivers, an unnecessary high latency overhead is introduced such as when transferring a 512-byte filter data coefficients to configure a 128-tap FIR filter. In this dissertation, a highly efficient, low latency command-status packet tunneling architecture built on top of the 25 Gbps Interlaken serial protocol for multi-gigabit inter-FPGA data streaming is proposed. Simulation results show that the proposed architecture works successfully with a high efficiency, utilizes only 13.21% and 10.34% of the clock cycles required in the conventional SPI and I2C implementations respectively. The proposed architecture also maintains a backward compatibility with control links implemented separately using SPI or I2C serial protocols to simplify the overall system design, reduce product development risks and system costs

Sistemas de teste automáticos para transceivers NG-PON2

Optical communications have had a fundamental role in conecting people worldwide. More than ever, there has been an incessant necessity to turn technology more ubiquitous With recent advancements in optical technology, it has become possible to keep up with the demand for higher transmission rates in upstream or downstream, higher bandwidth e still guaranteeing Quality of Service (QoS) among inumerous users This emerging necessity has taken telecommunication companies to inovate in the area of development regarding optical equipment and also dealing with the referred necessities. For this to happen, good quality control, calibration e testing of produced parts is of paramount importance. The work cut out for this dissertation is focused on the improvement and addition of funtionalities to a test-board designed to perform measurements of BER levels, calibration and maintenance of parts according to the newest optical standard(New Gigabit Passive Optical Network 2 (NGPON2)) that operates in maximum rates of 10Gb/s per channel. In the rst part of this work, emphasis is given to the development of a slave Inter Integrated Circuit (I2C) module that ensures connection between the test board and the user, supplying BER values measured through a block dedicated to measure BER levels. Later the same module will allow to access all micro-controlers of the test-board, ensuring calibration functions. On a second part, a characterization of different transceivers of different Field Programmable Gate Array (FPGA)s is performed, consisting of an eye diagram analysis of the transceivers and if possible, to test 10Gb/s continuous mode through BER curves assessing their response. Finally, a comparison is made between all transceivers, the obtained response along with all the respective results, will contribute to the source project of the automatic test board developed at PICadvanced with the intent on evaluating 10 Gigabit Small Form Factor Pluggables (XFP) production.As comunicações têm vindo a ter um papel fundamental em interligar todas as pessoas do mundo. Mais do que nunca, tem havido uma incessante necessidade de tornar a tecnologia mais ubíqua. Com o recente avanço e desenvolvimento da tecnologia Optica, tem sido possível acompanhar a demanda por altas taxas de transmissão em upstream ou downstream, maior largura de banda e ainda garantir Quality of Service (QoS) entre ínumeros utilizadores, etc. . . Esta necessidade emergente tem levado empresas de telecomunicações a inovar na área de desenvolvimento de equipamento óptico e por consequente, comaltar as necessidades referidas. Para isto acontecer tem de haver um bom controlo, calibração e teste de peças produzidas. O trabalho desta dissertação dedica-se ao melhoramento e acrescento de funcionalidades a uma placa de testes desenhada para desempenhar medições de níveis de Bit Error Ratio (BER), calibração e manutenção de peças para o novo standard óptico (New Gigabit Passive Optical Network 2 (NGPON2)) que recorre ao uso de taxas máximas de transmissão de 10Gb/s por canal Na primeira parte do trabalho é dado foco ao desenvolvimento de um módulo escravo Inter Integrated Circuit (I2C) que visa estabelecer o contacto entre a placa de calibração e o utilizador fornecendo os valores de BER medidos através de um bloco dedicado a medir o nível de BER. Mais tarde este módulo servirá para poder aceder aos micro-circuitos da placa de testes podendo realizar funções de calibração. Numa segunda parte, é realizada uma caracterização de diferentes transceivers de diferentes Field Programmable Gate Array (FPGA)s, a caracterização consiste numa análise do diagram de olho de transceivers e ainda sendo possível, testar o modo contínuo nas mesmas, através curvas de BER para avaliar a sua resposta. Por fim, é feita uma comparação entre os mesmos transceivers, além de que todos os resultados obtidos irão contribuir para a o projecto fonte da placa de testes automatizada desenvolvida pela PICadvanced com o intuito de avaliar a produção de 10 Gigabit Small Form Factor Pluggables (XFP).Mestrado em Engenharia Eletrónica e Telecomunicaçõe

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

A compact high-energy particle detector for low-cost deep space missions

Over the last few decades particle physics has led to many new discoveries, laying the foundation for modern science. However, there are still many unanswered questions which the next generation of particle detectors could address, potentially expanding our knowledge and understanding of the Universe. Owing to recent technological advancements, electronic sensors are now able to acquire measurements previously unobtainable, creating opportunities for new deep-space high-energy particle missions. Consequently, a new compact instrument was developed capable of detecting gamma rays, neutrons and charged particles. This instrument combines the latest in FPGA System-on-Chip technology as the central processor and a 3x3 array of silicon photomultipliers coupled with an organic plastic scintillator as the detector. Using modern digital pulse shape discrimination and signal processing techniques, the scintillator and photomultiplier combination has been shown to accurately discriminate between the di_erent particle types and provide information such as total energy and incident direction. The instrument demonstrated the ability to capture 30,000 particle events per second across 9 channels - around 15 times that of the U.S. based CLAS detector. Furthermore, the input signals are simultaneously sampled at a maximum rate of 5 GSPS across all channels with 14-bit resolution. Future developments will include FPGA-implemented digital signal processing as well as hardware design for small satellite based deep-space missions that can overcome radiation vulnerability

Evaluation of high-speed FPGA IO for inter-board communication

Growing demand for computation power requires high speed interconnects between FPGA devices. While there are multiple solutions available it is still challenging to choose one suited for the particular task. Is it therefore extremely import for both academic and industrial purposes to have access to real world performance evaluation of high speed interconnect technologies commonly offered on FPGAs. In this thesis we study the feasibility of high-speed interconnect and find that it is most relevant to evaluate the performance of LVDS and dedicated transceivers for board-to-board communication scenario. To address this requirement we design evaluation of a system implemented in Altera Cyclone V devices and conduct measurements of the transmission performance and resource usage. LVDS inter-board communication was implemented as point-to-point topology between two FPGA boards. The maximum received data rate is 823 Mbps per channel. On the base of the transceiver interface, the chain topology was created for communication of three devices. The maximum measured speed in the transceiver system is 1822 Mbps. The average logic utilization of the designs is about 3% of the FPGA resources. At the same time, 38% of the global clocks are used in the transceiver design. On the base of the performed experiments, we conclude that required high-speed interconnection can be implemented by establishing FPGA-to-FPGA communication via LVDS and the dedicated transceivers interfaces