A Practical Hardware Implementation of Systemic Computation

It is widely accepted that natural computation, such as brain computation, is far superior to typical computational approaches addressing tasks such as learning and parallel processing. As conventional silicon-based technologies are about to reach their physical limits, researchers have drawn inspiration from nature to found new computational paradigms. Such a newly-conceived paradigm is Systemic Computation (SC). SC is a bio-inspired model of computation. It incorporates natural characteristics and defines a massively parallel non-von Neumann computer architecture that can model natural systems efficiently. This thesis investigates the viability and utility of a Systemic Computation hardware implementation, since prior software-based approaches have proved inadequate in terms of performance and flexibility. This is achieved by addressing three main research challenges regarding the level of support for the natural properties of SC, the design of its implied architecture and methods to make the implementation practical and efficient. Various hardware-based approaches to Natural Computation are reviewed and their compatibility and suitability, with respect to the SC paradigm, is investigated. FPGAs are identified as the most appropriate implementation platform through critical evaluation and the first prototype Hardware Architecture of Systemic computation (HAoS) is presented. HAoS is a novel custom digital design, which takes advantage of the inbuilt parallelism of an FPGA and the highly efficient matching capability of a Ternary Content Addressable Memory. It provides basic processing capabilities in order to minimize time-demanding data transfers, while the optional use of a CPU provides high-level processing support. It is optimized and extended to a practical hardware platform accompanied by a software framework to provide an efficient SC programming solution. The suggested platform is evaluated using three bio-inspired models and analysis shows that it satisfies the research challenges and provides an effective solution in terms of efficiency versus flexibility trade-off

Autotuning the Intel HLS Compiler using the Opentuner Framework

High level synthesis (HLS) tools can be used to improve design flow and decrease verification times for field programmable gate array (FPGA) and application specific integrated circuit (ASIC) design. The Intel HLS Compiler is a high level synthesis tool that takes in untimed C/C++ as input and generates production-quality register transfer level (RTL) code that is optimized for Intel FPGAs. The translation does, however, require multiple iterations and manual optimizations to get comparable synthesized results to that of a solution written in a hardware descriptive language. The synthesis results can vary greatly based upon coding style and optimization techniques, and typically require an in-depth knowledge of FPGAs to fully optimize the translation which limits the audience of the tool. The extra abstraction that the C/C++ source code presents can also make it difficult to meet more specific design requirements; this includes designs to meet specific resource usage or performance based metrics. To improve the quality of results generated by the Intel HLS Compiler without a manual iterative process that requires an in-depth knowledge of FPGAs, this research proposes a method of automating some of the optimization techniques that improve the synthesized design through an autotuning process. The proposed approach utilizes the PyCParser library to parse C source files and the OpenTuner Framework to autotune the synthesis to provide a method that generates results that better meet the needs of the designer's requirements through lower FPGA resource usage or increased design performance. Such functionality is not currently available in Intel's commercial tools. The proposed approach was tested with the CHStone Benchmarking Suite of C programs as well as a standard digital signal processing finite impulse response filter. The results show that the commercial HLS tool can be automatically autotuned through placeholder injection using a source parsing tool for C code and using the OpenTuner Framework to autotune the results. For designs that are small in nature and include conducive structures to be autotuned, the results indicate resource usage reductions and/or performance increases of up to 40% as compared to the default Intel HLS Compiler results. The method developed in this research also allows additional design targets to be specified through the autotuner for consideration in the synthesized design which can yield results that are better matched to a design's requirements

Development and Application of Software to Understand 3D Chromatin Structure and Gene Regulation

Nearly all cells contain the same 2 meters of DNA that must be systematically organized into their nucleus for timely access to genes in response to stimuli. Proteins and biomolecular condensates make this possible by dynamically shaping chromatin into 3D structures that connect regulators to their genes. Chromatin loops are structures that are partly responsible for forming these connections and can result in disease when disrupted or aberrantly formed. In this work, I describe three studies centered on using 3D chromatin structure to understand gene regulation. Using multi-omic data from a macrophage activation time course, we show that regulation temporally precedes gene expression and that chromatin loops play a key role in connecting enhancers to their target genes. In the next study, we investigated the role of biomolecular condensates in loop formation by mapping 3D chromatin structure in cell lines before and after disruption of NUP98-HOXA9 condensate formation. Differential analysis revealed evidence of CTCF-independent loop formation sensitive to condensate disruption. In the last study, we used 3D chromatin structure and multi-omic data in chondrocytes to link variant-gene pairs associated with Osteoarthritis (OA). Computational analysis suggests that a specific variant may disrupt transcription factor binding and misregulate inflammatory pathways in OA. To carry out these analyses I built computational pipelines and two R/Bioconductor packages to support the processing and analysis of genomic data. The nullranges package contains functions for performing covariate-matched subsampling to generate null-hypothesis genomic data and mitigate the effects of confounding. The mariner package is designed for working with large chromatin contact data. It extends existing Bioconductor tools to allow fast and efficient extraction and manipulation of chromatin interactions for better understanding 3D chromatin structure and its impact on gene regulation.Doctor of Philosoph

High Performance Reconfigurable Fuzzy Logic Device for Medical Risk Evaluation

To date cardiovascular diseases (CVD) account for approximately 35% of all deaths worldwide. Many of these deaths are preventable if the risk of developing them can be accurately assessed early. Medical devices in use today cannot determine a patient's risk of developing a CVD condition. If accurate risk assessment was readily available to doctors, they can track rising trends in risk levels and recommend preventative measures for their patients. If patients had this risk assessment information before symptoms developed or life-threatening conditions occurred, they can contact their doctors to inquire about recommendations or seek help in emergency situations.This thesis research proposes the idea of using evolutionary programmed and tuned fuzzy logic controllers to diagnose a patient's risk of developing a CVD condition. The specific aim of this research seeks to advance the flexibility and functionality of fuzzy logic systems without sacrificing high speed and low resource utilization. The proposed system can be broken down into two layers. The bottom layer contains the controller that implements the fuzzy logic model and calculates the patient's risk of developing a CVD. The controller is designed in a context switchable hardware architecture the can be reconfigured to assess the risk of different CVD diseases. The top layer implements the evolutionary genetic algorithm in software, which configures the fuzzy parameters that optimize the behavior of the controller. The current implementation inputs patient's personal data such as electrocardiogram (ECG) wave features, age and body mass index (BMI) and outputs a risk percentage for Sinus Bradycardia (SB), a common cardiac arrhythmia. We validated this system via Matlab and Modelsim simulations and built the first prototype on a Xilinx Virtex-5 FPGA platform. Experimental results show that this 3-input-1-output fuzzy controller with 5 fuzzy sets per variable and 125 rule propositions produces results within an interval of approximately 1us while reducing hardware resource utilization by at least 25% when compared with existing designs

Methods to improve the reliability and resiliency of near/sub-threshold digital circuits

Energy consumption is one of the primary bottlenecks to both large and small scale modern compute platforms. Reducing the operating voltage of digital circuits to voltages where the supply voltage is near or below the threshold of the transistors has recently gained attention as a method to reduce the energy required for computations by as much as 6 times. However, when operating at near/sub-threshold voltages (where the supply voltage is near or below the threshold of the transistors), imperfections in transistor manufacturing, changes in temperature, and other difficult-to-predict factors cause wide variations in the timing of Complementary Metal-Oxide Semiconductor (CMOS) circuits due to an increased sensitivity at lower voltages. These increased variations result in poor aggregate performance and cause increased rates of error occurrence in computation. This work introduces several new methods to improve the reliability of near/sub-threshold circuits. The first is a design automation technique that is used to aid in low-voltage digital standard cell synthesis. Second, two circuit-level techniques are also introduced that aim to improve the reliability and resiliency of digital circuits by means of completion/error detection. These techniques are shown to improve speed and lower energy consumption at low overheads compared to previous methods. Most importantly, these circuit-level methods are specifically designed to operate at low voltages and can themselves tolerate variations and operation in harsh environments. Finally, a test-chip prototype designed in 65nm-CMOS demonstrates the practicality and feasibility of a proposed current sensing error detector

Programmable stochastic processors

As traditional approaches for reducing power in microprocessors are being exhausted, extreme power challenges call for unconventional approaches to power reduction. Recent research has shown substantial promise for application-specific stochastic computing, i.e., computing that exploits application error tolerance to enable careful relaxation of correctness guarantees provided by hardware in order to reduce power. This dissertation explores the feasibility, challenges, and potential benefits of stochastic computing in the context of programmable general purpose processors. Specifically, the dissertation describes design-level techniques that minimize the power of a processor for a non-zero error rate or allow a processor to fail gracefully when operated over a range of non-zero error rates. It presents microarchitectural design principles that allow a processor to trade off reliability and energy more efficiently to minimize energy when exploiting error resilience. It demonstrates the benefit of using compiler optimizations that optimize a binary to enable more energy savings when operating at a non-zero error rate. It also demonstrates significant benefits for a programmable stochastic processor prototype that improves energy efficiency by carefully relaxing correctness and exposing errors in applications running on a commodity processor. This dissertation on programmable stochastic processors conclusively shows that the architecture and design of processors and applications should be approached differently in scenarios where errors are allowed to be exposed from the hardware to higher levels of the compute stack. Significant energy benefits are demonstrated for design-, architecture-, compiler-, and application-level optimizations for general purpose programmable stochastic processors