A memory-based programmable logic device using look-up table cascade with synchronous static random access memories

A large-scale memory-technology-based programmable logic device (PLD) using LUT (Look-Up Table) cascade is developed in 0.35um Standard CMOS logic process. Eight 64K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) flexible cascade connection structure, 2) multi-phase pseudo-asynchronous operations with synchronous SRAM cores, 3) LUT-bypass redundancy. This chip operates at 33MHz in 8-LUT cascades with 122mW. Benchmark results show that it achieves a comparable performance to FPGAs

Programmable logic device with an 8-stage cascade of 64K-bit asynchronous SRAMs

The first implementation of a new programmable logic device using LUT(Look-Up Table) cascade architecture is developed in 0.35um CMOS logic process. Eight 64Kb asynchronous SRAMs are simply connected to form an LUT cascade with a few additional circuits. Benchmark results show that it has a competitive performance to FPGAs.IEEE Symposium on Low-Power and High-Speed Chips (Cool Chips VIII), April 22-25, 2005, Yokohama, Japa

A memory-based programmable logic device using a look-up table cascade with synchronous SRAMs

2005 International Conference on Solid State Devices and Materials (SSDM 2005), September13-15, 2005, Kobe, Hyogo, Japa

A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals

A Field Programmable Sequencer and Memory (FPSM), which is a programmable unit exclusively optimized for peripherals on a micro controller unit, is proposed. The FPSM functions as not only the peripherals but also the standard built-in memory. The FPSM provides easier programmability with a smaller area overhead, especially when compared with the FPGA. The FPSM is implemented on the FPGA and the programmability and performance for basic peripherals such as the 8 bit counter and 8 bit accuracy Pulse Width Modulation are emulated on the FPGA. Furthermore, the FPSM core with a 4K bit SRAM is fabricated in 0.18µm 5 metal CMOS process technology. The FPSM is an half the area of FPGA, its power consumption is less than one-fifth.Embargo Period 6 month

メモリをベースとしたマイコン用再構成可能デバイスとその応用に関する研究

13301甲第4625号博士（工学）金沢大学博士論文本文Ful

A Fast Logic Simulator Using a Look Up Table Cascade Emulator

Abstract — This paper shows a new type of a cycle-based logic simulation method using a Look-Up Table (LUT) cascade emulator. The method first transforms a given circuit into LUT cascades through BDD (Binary Decision Diagram). Then, it stores LUT data to the memory of an LUT cascade emulator. Next, it generates the C code representing the control circuit of the LUT cascade emulator. And, finally, it converts the C code into the execution code. This method is compared with a Levelized Compiled Code (LCC) simulator with respect to the simulation time and setup time. Although we used standard PC to simulate the circuit, experimental results show that this method is 12-64 times faster than the LCC. I

Programmable numerical function generators: Architectures and synthesis system

FPL2005, Tampere, Aug.24-26, 2005, pp.118-123.This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.This paper presents an architecture and a synthesis method for programmable numerical function generators of trigonometric functions, logarithm functions, square root, reciprocal, etc. Our architecture uses an LUT (Look-Up Table) cascade as the segment index encoder, compactly realizes various numerical functions, and is suitable for automatic synthesis. We have developed a synthesis system that converts MATLAB-like specification into HDL code. We propose and compare three architectures implemented as a FPGA (Field-Programmable Gate Array). Experimental results show the efficiency of our architecture and synthesis system

Programmable logic device with an 8-stage cascade of 64K-bit asynchronous SRAMs

The first implementation of a new programmable logic device using LUT(Look-Up Table) cascade architecture is developed in 0.35um CMOS logic process. Eight 64Kb asynchronous SRAMs are simply connected to form an LUT cascade with a few additional circuits. Benchmark results show that it has a competitive performance to FPGAs.IEEE Symposium on Low-Power and High-Speed Chips (Cool Chips VIII), April 22-25, 2005, Yokohama, Japa

A Memory-Based Programmable Logic Device Using a Look-Up Table Cascade with Synchronous SRAMs

2005 International Conference on Solid State Devices and Materials (SSDM 2005), September13-15, 2005, Kobe, Hyogo, Japa