20,535 research outputs found
Logic circuits from zero forcing
We design logic circuits based on the notion of zero forcing on graphs; each gate of the circuits is a gadget in which zero forcing is performed. We show that such circuits can evaluate every monotone Boolean function. By using two vertices to encode each logical bit, we obtain universal computation. We also highlight a phenomenon of âback forcingâ as a property of each function. Such a phenomenon occurs in a circuit when the input of gates which have been already used at a given time step is further modified by a computation actually performed at a later stage. Finally, we show that zero forcing can be also used to implement reversible computation. The model introduced here provides a potentially new tool in the analysis of Boolean functions, with particular attention to monotonicity. Moreover, in the light of applications of zero forcing in quantum mechanics, the link with Boolean functions may suggest a new directions in quantum control theory and in the study of engineered quantum spin systems. It is an open technical problem to verify whether there is a link between zero forcing and computation with contact circuits
Digital frequency discriminator Patent
Describing frequency discriminator using digital logic circuits and supplying single binary output signa
Holding Dissapearance in RTD-based Quantizers
Multiple-valued Logic (MVL) circuits are one of the most attractive
applications of the Monostable-to-Multistable transition Logic (MML), and they
are on the basis of advanced circuits for communications. The operation of such
quantizer has two steps : sampling and holding. Once the quantizer samples the
signal, it must maintain the sampled value even if the input changes. However,
holding property is not inherent to MML circuit topologies. This paper analyses
the case of an MML ternary inverter used as a quantizer, and determines the
relations that circuit representative parameters must verify to avoid this
malfunction.Comment: Submitted on behalf of TIMA Editions
(http://irevues.inist.fr/tima-editions
MULTIPAC, a multiple pool processor and computer for a spacecraft central data system, phase 2 Final report
MULTIPAC, multiple pool processor and computer for deep space probe central data syste
The Rolf of Test Chips in Coordinating Logic and Circuit Design and Layout Aids for VLSI
This paper emphasizes the need for multipurpose test chips and comprehensive procedures for use in supplying accurate input data to both logic and circuit simulators and chip layout aids. It is shown that the location of test structures within test chips is critical in obtaining representative data, because geometrical distortions introduced during the photomasking process can lead to
significant intrachip parameter variations. In order to transfer test chip designs quickly, accurately, and economically, a commonly accepted portable chip layout notation and commonly accepted parametric tester language are needed. In order to measure test chips more accurately and more rapidly, parametric testers with improved architecture need to be developed in conjunction with
innovative test structures with on-chip signal conditioning
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