Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER

Impact of parameter variations on circuits and microarchitecture

Parameter variations, which are increasing along with advances in process technologies, affect both timing and power. Variability must be considered at both the circuit and microarchitectural design levels to keep pace with performance scaling and to keep power consumption within reasonable limits. This article presents an overview of the main sources of variability and surveys variation-tolerant circuit and microarchitectural approaches.Peer ReviewedPostprint (published version

Asynchronous Data Processing Platforms for Energy Efficiency, Performance, and Scalability

The global technology revolution is changing the integrated circuit industry from the one driven by performance to the one driven by energy, scalability and more-balanced design goals. Without clock-related issues, asynchronous circuits enable further design tradeoffs and in operation adaptive adjustments for energy efficiency. This dissertation work presents the design methodology of the asynchronous circuit using NULL Convention Logic (NCL) and multi-threshold CMOS techniques for energy efficiency and throughput optimization in digital signal processing circuits. Parallel homogeneous and heterogeneous platforms implementing adaptive dynamic voltage scaling (DVS) based on the observation of system fullness and workload prediction are developed for balanced control of the performance and energy efficiency. Datapath control logic with NULL Cycle Reduction (NCR) and arbitration network are incorporated in the heterogeneous platform for large scale cascading. The platforms have been integrated with the data processing units using the IBM 130 nm 8RF process and fabricated using the MITLL 90 nm FDSOI process. Simulation and physical testing results show the energy efficiency advantage of asynchronous designs and the effective of the adaptive DVS mechanism in balancing the energy and performance in both platforms

Design and Analysis of an Asynchronous Microcontroller

This dissertation presents the design of the most complex MTNCL circuit to date. A fully functional MTNCL MSP430 microcontroller is designed and benchmarked against an open source synchronous MSP430. The designs are compared in terms of area, active energy, and leakage energy. Techniques to reduce MTNCL pipeline activity and improve MTNCL register file area and power consumption are introduced. The results show the MTNCL design to have superior leakage power characteristics. The area and active energy comparisons highlight the need for better MTNCL logic synthesis techniques

Low Power Design Of Asynchronous Fine-Grain Power-Gated Logic

In technology improvement power dissipation has one of the major factor well known short circuit dissipations, leakage dissipations and dynamic switching dissipations are major power dissipation sources of CMOS Chips. For reducing power dissipation in CMOS logic blocks various techniques were there among these techniques most effective new technique implemented with low power dissipation. That is “low power design of Asynchronous fine-grain power gated logic”(LPAFPL). Low power AFPL is a new logic family. It consist of ECRL (efficient charge recovery logic gate), Pipeline system, C-element and Partial Charge Reuse mechanism (PCR). Each pipeline stage is comprised efficient charge recovery logic gate gains power and it is became active when useful computations are there and does not requires power at idle stage. Thus gives negligible leakage power dissipation. PCR is the output node of the ECRL logic, To evaluate the CMOS logic circuit level. Then it automatically reduced the power dissipation in complete evaluation of CMOS circuits

CAD Tools for Synthesis of Sleep Convention Logic

This dissertation proposes an automated flow for the Sleep Convention Logic (SCL) asynchronous design style. The proposed flow synthesizes synchronous RTL into an SCL netlist. The flow utilizes commercial design tools, while supplementing missing functionality using custom tools. A method for determining the performance bottleneck in an SCL design is proposed. A constraint-driven method to increase the performance of linear SCL pipelines is proposed. Several enhancements to SCL are proposed, including techniques to reduce the number of registers and total sleep capacitance in an SCL design

Design and Comparison of Asynchronous FFT Implementations

Fast Fourier Transform (FFT) is a widely used digital signal processing technology in a large variety of applications. For battery-powered embedded systems incorporating FFT, its physical implementation is constrained by strict power consumption, especially during idle periods. Compared to the prevailing clocked synchronous counterpart, quasi-delay insensitive asynchronous circuits offer a series of advantages including flexible timing requirement and lower leakage power, making them ideal choices for these systems. In this thesis work, various FFT configurations were implemented in the low-power Multi-Threshold NULL Convention Logic (MTNCL) paradigm. Analysis illustrates the area and power consumption trends along the changing of the number of points, data widths, and the number of pipeline stages

Design and Comparison of Asynchronous FFT Implementations

Fast Fourier Transform (FFT) is a widely used digital signal processing technology in a large variety of applications. For battery-powered embedded systems incorporating FFT, its physical implementation is constrained by strict power consumption, especially during idle periods. Compared to the prevailing clocked synchronous counterpart, quasi-delay insensitive asynchronous circuits offer a series of advantages including flexible timing requirement and lower leakage power, making them ideal choices for these systems. In this thesis work, various FFT configurations were implemented in the low-power Multi-Threshold NULL Convention Logic (MTNCL) paradigm. Analysis illustrates the area and power consumption trends along the changing of the number of points, data widths, and the number of pipeline stages

Analysis of Parameter Tuning on Energy Efficiency in Asynchronous Circuits

Power and energy consumption are the primary concern of the digital integrated circuit (IC) industry. Asynchronous logic, in the past several years, has increased in popularity due to its low power nature. This thesis analyzes a collection of array multipliers with different parameters to compare two asynchronous design paradigms, NULL Convention Logic (NCL) and Multi-Threshold NULL Convention Logic (MTNCL). Several commercially available pieces of software and custom scripts are used to analyze the asynchronous circuits and their components to provide the energy consumption estimation on various parts of each circuit. The analysis of the software results revealed that MTNCL circuits are more energy efficient for any size provided the number of pipeline stages does not become too great. Otherwise NCL would consume less energy. A combinational logic gate count to register gate count ratio of 3 was given to help determine when an MTNCL circuit would have too many pipeline stages for circuits designed with IBM\u27s 130nm 8RF-DM design kit