dRail: a novel physical layout methodology for power gated circuits

In this paper we present a physical layout methodology, called dRail, to allow power gated and non-power gated cells to be placed next to each other. This is unlike traditional voltage area layout which separates cells to prevent shorting of power supplies leading to impact on area, routing and power. To implement dRail, a modified standard cell architecture and physical layout is proposed. The methodology is validated by implementing power gating on the data engine in an ARM Cortex-A5 processor using a 65nm library, and shows up to 38% reduction in area cost when compared to traditional voltage area layou

Ultra low power mixer with out-of-band RF energy harvesting for wireless sensor networks applications

An ultra low power mixer with out-of-band radio frequency (RF) energy harvesting suitable for the wireless sensors network (WSN) application is proposed in this paper. The presented mixer is able to harvest the out-of-band RF energy and keep it working in ultra low power condition and extend the battery life of the WSN. The mixer is designed and simulated with Global Foundries ’ 0.18 μ m CMOS RF process, and it operates at 2.4GHz industrial, scientific, and medical (ISM) band. The Cadence IC Design Tools post-layout simulation results demonstrate that the proposed mixer consumes 248 μ W from a 1V supply voltage. Furthermore, the power consumption can be reduced to 120.8 μ W by the out-of-band RF energy harvesting rectifier

A built-in self-test module for 16-bit parallel photon counting circuit using 180 nm CMOS process

This study investigated the use of a built-in-self-test (BIST) module detecting catastrophic errors in photon-counter accumulator for liquid contamination level measurement. Efficient algorithms are exceptionally demanded for a high-count rate and low voltage system photon counting circuit on-chip. The photon counter sensors are also required high sensitivity digital counter that encodes the arrival of photon in precise timing to prevent any count erroring the absence of light. The proposed BIST is integrated on the data acquisition system, where the accumulator is located. The design circuit, functionality and topology tests of BIST and circuit under test are realized with 180 nm Silterra CMOS Process. The same Verilog codes are verified using field programmable gate array (FPGA) to predict the hardware functionality prior fabrication. The measurement was able to detect at least 90 % fault coverage within 16-bit data acquisition system at minimum operating frequency of 166.7 MHz

A Review on Semiconductors Including Applications and Temperature Effects in Semiconductors

There is no doubt that semiconductors changed the world beyond anything that could have been imagined before them. Although people have probably always needed to communicate and process data, it is thanks to the semiconductors that these two important tasks have become easy and take up infinitely less time than, e.g., at the time of vacuum tubes. Semiconductor materials are the building blocks of the entire electronics and computer industry. Small, lightweight, high speed, and low power consumption devices would not be possible without integrated circuits (chips), which consist of semiconductor materials. This paper provides a general discussion of semiconductor materials, their history, classification and the temperature effects in semiconductors. In this section we provide details about the impact of temperature on the MOSFET energy band gap, carrier density, mobility, carrier diffusion, velocity saturation, current density, threshold voltage, leakage current and interconnect resistance. We also provide the applications of semiconductor materials in different sectors of modern electronics and communications.

Methodology for Standby Leakage Power Reduction in Nanometer-Scale CMOS Circuits

In nanometer-scale CMOS technology, leakage power has become a major component of the total power dissipation due to the downscaling of threshold voltage and gate oxide thickness. The leakage power consumption has received even more attention by increasing demand for mobile devices. Since mobile devices spend a majority of their time in a standby mode, the leakage power savings in standby state is critical to extend battery lifetime. For this reason, low power has become a major factor in designing CMOS circuits. In this dissertation, we propose a novel transistor reordering methodology for leakage reduction. Unlike previous technique, the proposed method provides exact reordering rules for minimum leakage formation by considering all leakage components. Thus, this method formulates an optimized structure for leakage reduction even in complex CMOS logic gate, and can be used in combination with other leakage reduction techniques to achieve further improvement. We also propose a new standby leakage reduction methodology, leakage-aware body biasing, to overcome the shortcomings of a conventional Reverse Body Biasing (RBB) technique. The RBB technique has been used to reduce subthreshold leakage current. Therefore, this technique works well under subthreshold dominant region even though it has intrinsic structural drawbacks. However, such drawbacks cannot be overlooked anymore since gate leakage has become comparable to subthreshold leakage in nanometer-scale region. In addition, BTBT leakage also increases with technology scaling due to the higher doping concentration applied in each process technology. In these circumstances, the objective of leakage minimization is not a single leakage source but the overall leakage sources. The proposed leakage-aware body biasing technique, unlike conventional RBB technique, considers all major leakage sources to minimize the negative effects of existing body biasing approach. This can be achieved by intelligently applying body bias to appropriate CMOS network based on its status (on-/off-state) with the aid of a pin/transistor reordering technique

RFIC piirin digitaaliohjaukseen vaadittavien piirirakenteiden suunnittelu

Tiivistelmä. Tässä työssä suunnitellaan 22 nm FD-SOI-prosessille digitaalikirjaston osa, jolla voidaan toteuttaa tarvittava ohjaus RFIC-komponenttilohkoille. Komponenteista rakennetaan mahdollisimman pieniä ja nopeita käyttäen matalan kynnysjännitteen transistoreja. Työssä tarvittavan digitaalisen ohjauksen luomiseksi tehdään NAND-, NOR-, AND- ja NOT-portit sekä siirtorekistereitä, osoitedekooderi, virta-DAC ja D-kiikku. Piirikaaviot ja -kuviot suunnitellaan Cadencen Virtuoso-ohjelmistolla ja simuloinnit tehdään Cadencen ADE-simulointiympäristössä. Simulointien avulla mitoitetaan digitaalilohkot ja varmistetaan niiden toiminta. Testipenkkeihin luodaan lohkoille mahdollisimman todenmukainen ympäristö käyttäen viivästettyjä ja noin 5 ps nousu- ja laskuajoilla olevia signaaleja sekä kuormana 5 minimikokoista invertteriä. Tehonkulutus ja pinta-ala minimoidaan suunnittelemalla mahdollisimman nopeita ja pieniä piirejä ja käyttäen vain muutamaa alinta metallikerrosta piirikuviossa. Transistoreja yhdistelemällä piirin pinta-alaa saadaan parhaissa tapauksissa pienennettyä yli 50%. Simuloinneissa nähdään, että komponenttien tehonkulutus ja teknologian tuomat virtarajoitukset eivät tuota ongelmia, sillä komponenttien maksimivirrat pysyvät alle 500 µA. Lisäksi simuloinneissa tulee esille logiikkakomponenttien kyky vaimentaa kohinaa ja kapasitiivisen kuormituksen vaikutus virtaan ja viiveeseen. Lopuksi valmiit komponentit simuloidaan vielä RFIC-lohkon kanssa piirikaaviotasolla ekstraktoitujen parasiittisten vaikutus huomioiden.Design of circuit blocks for digital control of integrated RF circuit. Abstract. The aim of this work is to design a part of a digital component library using 22 nm FDSOI CMOS process, which could be used to digitally control analog RFIC-blocks. Low threshold voltage transistors are used in order to create as small and fast components as possible. In this work NAND, NOR, AND and NOT logic ports are designed together with shift registers, address decoder, current-DAC and D-flipflop. Schematics and layouts are designed by using Cadence Virtuoso software and simulations are done by using Cadence ADE -simulation environment. Simulations are used to size logic components and verify operations. A realistic operation environment is created by using delayed signals with 5 ps rise and fall times and a load of 5 minimum size inverters. Power consumption and area of circuits are minimized by designing fast and small circuits and by using only a few of the bottom metal layers in layouts. In the best cases the area is reduced more than 50 percent by combining transistor structures. In simulations power consumption and current constraints imposed by used technology are not a problem due to smaller than 500 µA maximum currents of components. In addition, the simulations show the ability of logic components to attenuate noise and how the capacitive load affects to the current consumption and delay of components. Finally, implemented components are simulated with actual RFIC-blocks at schematic level by considering the effects of extracted parasitic components

It is too hot in here! A performance, energy and heat aware scheduler for Asymmetric multiprocessing processors in embedded systems.

Modern architecture present in self-power devices such as mobiles or tablet computers proposes the use of asymmetric processors that allow either energy-efficient or performant computation on the same SoC. For energy efficiency and performance consideration, the asymmetry resides in differences in CPU micro-architecture design and results in diverging raw computing capability. Other components such as the processor memory subsystem also show differences resulting in different memory transaction timing. Moreover, based on a bus-snoop protocol, cache coherency between processors comes with a peculiarity in memory latency depending on the processors operating frequencies. All these differences come with challenging decisions on both application schedulability and processor operating frequencies. In addition, because of the small form factor of such embedded systems, these devices generally cannot afford active cooling systems. Therefore thermal mitigation relies on dynamic software solutions. Current operating systems for embedded systems such as Linux or Android do not consider all these particularities. As such, they often fail to satisfy user expectations of a powerful device with long battery life. To remedy this situation, this thesis proposes a unified approach to deliver high-performance and energy-efficiency computation in each of its flavours, considering the memory subsystem and all computation units available in the system. Performance is maximized even when the device is under heavy thermal constraints. The proposed unified solution is based on accurate models targeting both performance and thermal behaviour and resides at the operating systems kernel level to manage all running applications in a global manner. Particularly, the performance model considers both the computation part and also the memory subsystem of symmetric or asymmetric processors present in embedded devices. The thermal model relies on the accurate physical thermal properties of the device. Using these models, application schedulability and processor frequency scaling decisions to either maximize performance or energy efficiency within a thermal budget are extensively studied. To cover a large range of application behaviour, both models are built and designed using a generative workload that considers fine-grain details of the underlying microarchitecture of the SoC. Therefore, this approach can be derived and applied to multiple devices with little effort. Extended evaluation on real-world benchmarks for high performance and general computing, as well as common applications targeting the mobile and tablet market, show the accuracy and completeness of models used in this unified approach to deliver high performance and energy efficiency under high thermal constraints for embedded devices