Algorithmic studies on PCB routing

As IC technology advances, the package size keeps shrinking while the pin count of a package keeps increasing. A modern IC package can have a pin count of thousands. As a result, a complex printed circuit board (PCB) can host more than ten thousand signal nets. Such a huge pin count and net count make manual design of packages and PCBs an extremely time-consuming and error-prone task. On the other hand, increasing clock frequency imposes various physical constraints on PCB routing. These constraints make traditional IC and PCB routers not applicable to modern PCB routing. To the best of our knowledge, there is no mature commercial or academic automated router that handles these constraints well. Therefore, automated PCB routers that are tuned to handle such constraints become a necessity in modern design. In this dissertation, we propose novel algorithms for three major aspects of PCB routing: escape routing, area routing and layer assignment. Escape routing for packages and PCBs has been studied extensively in the past. Network flow is pervasively used to model this problem. However, previous studies are incomplete in two senses. First, none of the previous works correctly model the diagonal capacity, which is essential for 45 degree routing in most packages and PCBs. As a result, existing algorithms may either produce routing solutions that violate the diagonal capacity or fail to output a legal routing even though one exists. Second, few works discuss the escape routing problem of differential pairs. In high-performance PCBs, many critical nets use differential pairs to transmit signals. How to escape differential pairs from a pin array is an important issue that has received too little attention in the literature. In this dissertation, we propose a new network flow model that guarantees the correctness when diagonal capacity is taken into consideration. This model leads to the first optimal algorithm for escape routing. We also extend our model to handle missing pins. We then propose two algorithms for the differential pair escape routing problem. The first one computes the optimal routing for a single differential pair while the second one is able to simultaneously route multiple differential pairs considering both routability and wire length. We then propose a two-stage routing scheme based on the two algorithms. In our routing scheme, the second algorithm is used to generate initial routing and the first algorithm is used to perform rip-up and reroute. Length-constrained routing is another very important problem for PCB routing. Previous length-constrained routers all have assumptions on the routing topology. We propose a routing scheme that is free of any restriction on the routing topology. The novelty of our proposed routing scheme is that we view the length-constrained routing problem as an area assignment problem and use a placement structure to help transform the area assignment problem into a mathematical programming problem. Experimental results show that our routing scheme can handle practical designs that previous routers cannot handle. For designs that they could handle, our router runs much faster. Length-constrained routing requires the escaped nets to have matching ordering along the boundaries of the pin arrays. However, in some practical designs, the net ordering might be mismatched. To address this issue, we propose a preprocessing step to untangle such twisted nets. We also introduce a practical routing style, which we call single-detour routing, to simplify the untangling problem. We discover a necessary and sufficient condition for the existence of single-detour routing solutions and present a dynamic programming based algorithm that optimally solves the problem. By integrating our algorithm into the bus router in a length-constrained router, we show that many routing problems that cannot be solved previously can now be solved with insignificant increase in runtime. The nets on a PCB are usually grouped into buses. Because of the high pin density of the packages, the buses need to be assigned into multiple routing layers. We propose a layer assignment algorithm to assign a set of buses into multiple layers without causing any conflict. Our algorithm guarantees to produce a layer assignment with minimum number of layers. The key idea is to transform the layer assignment problem into a bipartite matching problem. This research result is an improvement over a previous work, which is optimal for only one layer

MulCh: a Multi-layer Channel Router using One, Two, and Three Layer Partitions

Chameleon, a channel router for three layers of interconnect, has been implemented to accept specification of an arbitrary number of layers. Chameleon is based on a strategy of decomposing the multilayer problem into two- and three-layer problems in which one of the layers is reserved primarily for vertical wire runs and the other layer(s) for horizontal runs. In some situations, however, it is advantageous to consider also layers that allow the routing of entire nets, using both horizontal and vertical wires. MulCh is a multilayer channel router that extends the algorithms of Chameleon in this direction. MulCh can route channels with any number of layers and automatically chooses a good assignment of wiring strategies to the different layers. In test cases, MulCh shows significant improvement over Chameleon in terms of channel width, net length, and number of vias

3D Global Router: a Study to Optimize Congestion, Wirelength and Via for Circuit Layout

The increasing size of integrated circuits and aggressive shrinking process feature size for IC manufacturing process poses signicant challenges on traditional physical design problems. Various design rules signicantly complicate the physical design problems and large problem size abides nothing but extremely e cient techniques. Leading physical design tools have to be powerful enough to handle complex design demands and be nimble enough to waste no runtime. This thesis studies the challenges faced by global routing problem, one of the traditional physical design problems that needs to be pushed to its new limit. This work proposes three e ective tools to tackle congestion, wire and via optimization in global routing process, from three di erent aspects. The number of vias generated during the global routing stage is a critical factor for the yield of integrated circuits. However, most global routers only approach the problem by charging a cost for vias in the maze routing cost function. The first work of this thesis, FastRoute 4.0 presents a global router that addresses the via number optimization problem throughout the entire global routing ow. It introduces the via aware Steiner tree generation, 3-bend routing and layer assignment with careful ordering to reduce via count. The integration of these three techniques with existing academic global routers achieves signicant reduction in via count without any sacrice in runtime. Despite of the recent development for popular rip-up and reroute framework, the congestion elimination process remains arbitrary and requires signicant tuning. Global routing has congestion elimination as the first and foremost priority and congestion issue becomes increasingly severe due to timing requirements, design for manufacturability. The second work of this thesis, an auction algorithm based pre-processing framework (APF) for global routing focuses on how to eliminate congestion e ectively. In order to achieve more consistent congestion elimination, the framework uses auction based detour techniques to alleviate the impacts of greedy sequential manner of maze routing, which remains as a major drawback in the most popular global routing framework. In the framework, APF first identies the most congested global routing locations by an interval over ow lower bound technique. Then APF uses auction based detour algorithm to compute which nets to detour and where to detour. The framework can be applied to any global routers and would help them to achieve signicant improvement in both solution quality and runtime. The third work in this thesis combines the advantage of the two framework used to minimize via usage in global routing: 3D routers with good solution quality and e cient 2D routers with layer assignment process. It results in a new multi-level 3D global router called MGR (multi-level global router) that combines the advantage of both kinds. MGR resorts to an e cient multi-level framework to reroute nets in the congested region on the 3D grid graph. Routing on the coarsened grid graph speeds up the global router while 3D routing introduces less vias. The powerful multi-level rerouting framework wraps three innovative routing techniques together: an adaptive resource reservation technique in coarsening process, a new 3-terminal maze routing algorithm and a network flow based solution propagation method in uncoarsening process. As a result, MGR can achieve the solution quality close to 3D routers with comparable runtime of 2D routers

On Energy Efficient Hierarchical Cross-Layer Design: Joint Power Control and Routing for Ad Hoc Networks

In this paper, a hierarchical cross-layer design approach is proposed to increase energy efficiency in ad hoc networks through joint adaptation of nodes' transmitting powers and route selection. The design maintains the advantages of the classic OSI model, while accounting for the cross-coupling between layers, through information sharing. The proposed joint power control and routing algorithm is shown to increase significantly the overall energy efficiency of the network, at the expense of a moderate increase in complexity. Performance enhancement of the joint design using multiuser detection is also investigated, and it is shown that the use of multiuser detection can increase the capacity of the ad hoc network significantly for a given level of energy consumption.Comment: To appear in the EURASIP Journal on Wireless Communications and Networking, Special Issue on Wireless Mobile Ad Hoc Network

Directed Placement for mVLSI Devices

Continuous-flow microfluidic devices based on integrated channel networks are becoming increasingly prevalent in research in the biological sciences. At present, these devices are physically laid out by hand by domain experts who understand both the underlying technology and the biological functions that will execute on fabricated devices. The lack of a design science that is specific to microfluidic technology creates a substantial barrier to entry. To address this concern, this article introduces Directed Placement, a physical design algorithm that leverages the natural "directedness" in most modern microfluidic designs: fluid enters at designated inputs, flows through a linear or tree-based network of channels and fluidic components, and exits the device at dedicated outputs. Directed placement creates physical layouts that share many principle similarities to those created by domain experts. Directed placement allows components to be placed closer to their neighbors compared to existing layout algorithms based on planar graph embedding or simulated annealing, leading to an average reduction in laid-out fluid channel length of 91% while improving area utilization by 8% on average. Directed placement is compatible with both passive and active microfluidic devices and is compatible with a variety of mainstream manufacturing technologies