A statistical study of time dependent reliability degradation of nanoscale MOSFET devices

Charge trapping at the channel interface is a fundamental issue that adversely affects the reliability of metal-oxide semiconductor field effect transistor (MOSFET) devices. This effect represents a new source of statistical variability as these devices enter the nano-scale era. Recently, charge trapping has been identified as the dominant phenomenon leading to both random telegraph noise (RTN) and bias temperature instabilities (BTI). Thus, understanding the interplay between reliability and statistical variability in scaled transistors is essential to the implementation of a ‘reliability-aware’ complementary metal oxide semiconductor (CMOS) circuit design. In order to investigate statistical reliability issues, a methodology based on a simulation flow has been developed in this thesis that allows a comprehensive and multi-scale study of charge-trapping phenomena and their impact on transistor and circuit performance. The proposed methodology is accomplished by using the Gold Standard Simulations (GSS) technology computer-aided design (TCAD)-based design tool chain co-optimization (DTCO) tool chain. The 70 nm bulk IMEC MOSFET and the 22 nm Intel fin-shape field effect transistor (FinFET) have been selected as targeted devices. The simulation flow starts by calibrating the device TCAD simulation decks against experimental measurements. This initial phase allows the identification of the physical structure and the doping distributions in the vertical and lateral directions based on the modulation in the inversion layer’s depth as well as the modulation of short channel effects. The calibration is further refined by taking into account statistical variability to match the statistical distributions of the transistors’ figures of merit obtained by measurements. The TCAD simulation investigation of RTN and BTI phenomena is then carried out in the presence of several sources of statistical variability. The study extends further to circuit simulation level by extracting compact models from the statistical TCAD simulation results. These compact models are collected in libraries, which are then utilised to investigate the impact of the BTI phenomenon, and its interaction with statistical variability, in a six transistor-static random access memory (6T-SRAM) cell. At the circuit level figures of merit, such as the static noise margin (SNM), and their statistical distributions are evaluated. The focus of this thesis is to highlight the importance of accounting for the interaction between statistical variability and statistical reliability in the simulation of advanced CMOS devices and circuits, in order to maintain predictivity and obtain a quantitative agreement with a measured data. The main findings of this thesis can be summarised by the following points: Based on the analysis of the results, the dispersions of VT and ΔVT indicate that a change in device technology must be considered, from the planar MOSFET platform to a new device architecture such as FinFET or SOI. This result is due to the interplay between a single trap charge and statistical variability, which has a significant impact on device operation and intrinsic parameters as transistor dimensions shrink further. The ageing process of transistors can be captured by using the trapped charge density at the interface and observing the VT shift. Moreover, using statistical analysis one can highlight the extreme transistors and their probable effect on the circuit or system operation. The influence of the passgate (PG) transistor in a 6T-SRAM cell gives a different trend of the mean static noise margin

Recent Advances in Thin Film Electronic Devices

This reprint is a collection of the papers from the Special Issue “Recent Advances in Thin Film Electronic Devices” in Micromachines. In this reprrint, 1 editorial and 11 original papers about recent advances in the research and development of thin film electronic devices are included. Specifically, three research fields are covered: device fundamentals (5 papers), fabrication processes (5 papers), and testing methods (1 paper). The experimental data, simulation results, and theoretical analysis presented in this reprint should benefit those researchers in flat panel displays, flat panel sensors, energy devices, memories, and so on

Experimental Characterization of Random Telegraph Noise and Hot Carrier Aging of Nano-scale MOSFETs

One of the emerging challenges in the scaling of MOSFETs is the reliability of ultra-thin gate dielectrics. Various sources can cause device aging, such as hot carrier aging (HCA), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and time dependent device breakdown (TDDB). Among them, hot carrier aging (HCA) has attracted much attention recently, because it is limiting the device lifetime. As the channel length of MOSFETs becomes smaller, the lateral electrical field increases and charge carriers become sufficiently energetic (“hot”) to cause damage to the device when they travel through the space charge region near the drain. Unlike aging that causes device parameters, such as threshold voltage, to drift in one direction, nano-scale devices also suffer from Random Telegraph Noise (RTN), where the current can fluctuate under fixed biases. RTN is caused by capturing/emitting charge carriers from/to the conduction channel. As the device sizes are reduced to the nano-meters, a single trap can cause substantial fluctuation in the current and threshold voltage. Although early works on HCA and RTN have improved the understanding, many issues remain unresolved and the aim of this project is to address these issues. The project is broadly divided into three parts: (i) an investigation on the HCA kinetics and how to predict HCA-induced device lifetime, (ii) a study of the interaction between HCA and RTN, and (iii) developing a new technique for directly measuring the RTN-induced jitter in the threshold voltage. To predict the device lifetime, a reliable aging kinetics is indispensable. Although early works show that HCA follows a power law, there are uncertainties in the extraction of the time exponent, making the prediction doubtful. A systematic experimental investigation was carried out in Chapter 4 and both the stress conditions and measurement parameters were carefully selected. It was found that the forward saturation current, commonly used in early work for monitoring HCA, leads to an overestimation of time exponents, because part of the damaged region is screened off by the space charges near the drain. Another source of errors comes from the inclusion of as-grown defects in the aging kinetics, which is not caused by aging. This leads to an underestimation of the time exponent. After correcting these errors, a reliable HCA kinetics is established and its predictive capability is demonstrated. There is confusion on how HCA and RTN interact and this is researched into in Chapter 5. The results show that for a device of average RTN, HCA only has a modest impact on RTN. RTN can either increase or decrease after HCA, depending on whether the local current under the RTN traps is rising or reducing. For a device of abnormally high RTN, RTN reduces substantially after HCA and the mechanism for this reduction is explored. The RTN-induced threshold voltage jitter, ∆Vth, is difficult to measure, as it is typically small and highly dynamic. Early works estimate this ∆Vth from the change in drain current and the accuracy of this estimation is not known. Chapter 6 focuses on developing a new ‘Trigger-When-Charged’ technique for directly measuring the RTN-induced ∆Vth. It will be shown that early works overestimate ∆Vth by a factor of two and the origin of this overestimation is investigated. This thesis consists of seven chapters. Chapter 1 introduces the project and its objectives. A literature review is given in Chapter 2. Chapter 3 covers the test facilities, measurement techniques, and devices used in this project. The main experimental results and analysis are given in Chapters 4-6, as described above. Finally, Chapter 7 concludes the project and discusses future works

Single Ion Impact Detection & Scanning Probe Aligned Ion Implantation for Quantum Bit Formation

Daten- und Informationsverarbeitung via Quantencomputer ist ein viel versprechender Ansatz, um die klassische Art und Weise via Digitalrechner, welche sich fundamentalen physikalischen Grenzen annŠhern, zu ersetzen. Anstelle von klassischen Bits werden Quantenbits (Qubits) fŸr Rechenoperationen verwendet. Aufgrund quantenmechanischer PhŠnomene wie Superposition und VerschrŠnkung, wird die Informationsverarbeitung in einer ganz anderen Art und Weise umgesetzt und eine Leistungssteigerung fŸr bestimmte Aufgabenstellungen erreicht. Es gibt verschiedene VorschlŠge zur technischen Umsetzung von Quanten-Bits. Unter ihnen sind Elektronen- oder Kernspins von Defektstellen in Festkšrpern. Zwei solche Kandidaten mit Spinfreiheitsgraden sind einzelne Donatoren in Silizium und Stickstoff Fehlstellen (NV) Zentren in Diamant. Beide Qubit-Kandidaten besitzen aussergewšhnliche Eigenschaften, welche sie zu vielversprechenden Bausteinen machen. Neben gewissen Vorteilen verbindet die beiden Qubits auch die Notwendigkeit, diese prŠzise in ihren TrŠgermaterialien und Bauelementstrukturen zu platzieren. Eine hŠufig verwendete Methode, die Fremdatome in die Substratmaterialien einzubringen, ist die Ionenimplantation. HierfŸr kšnnen fokussierte Ionenstrahl-Systeme verwendet werden, oder Kollimationstechniken, wie in dieser Arbeit. Ein ausgedehnter Ionenstrahl trifft die RŸckseite einer Rastersondenmikroskopspitze mit integrierten …ffnungen. Das Rastersondenmikroskop ermšglichen die zerstšrungsfreie und hochauflšsende Abbildung von Bauteilstrukturen und die Platzierung der Rastersondenmikroskopspitze, und damit des kollimierten Ionenstrahls, um ausgewŠhlte Regionen zu implantieren. In der vorgelegten Arbeit wird diese Technik angewendet und weiterentwickelt, um notwendige PrŠzisionskriterien zu erfŸllen. Die Platzierung des Ionenstrahls auf Bauelementstrukturen, welche empfindsam auf Ionenbombardement reagieren und damit Detektoren darstellen, wurde demonstriert. Die gleiche Technik wird auch zur Anordnung von NV-Zentren in Diamantsubstraten verwendet. Des weiteren werden einzelne IoneneinschlŠge in Siliziumbauteilen erfasst, wodurch das gezielte Dotieren Ion fŸr Ion ermšglicht wird.Quantum computing and quantum information processing is a promising path to replace classical information processing via conventional computers which are approaching fundamental physical limits. Instead of classical bits, quantum bits (qubits) are utilized for computing operations. Due to quantum mechanical phenomena such as superposition and entanglement, a completely different way of information processing is achieved, enabling enhanced performance for certain problem sets. Various proposals exist on how to realize a quantum bit. Among them are electron or nuclear spins of defect centers in solid state systems. Two such candidates with spin degree of freedom are single donor atoms in silicon and nitrogen vacancy (NV) defect centers in diamond. Both qubit candidates possess extraordinary qualities which makes them promising building blocks. Besides certain advantages, the qubits share the necessity to be placed precisely in their host materials and device structures. A commonly used method is to introduce the donor atoms into the substrate materials via ion implantation. For this, focused ion beam systems can be used, or collimation techniques as in this work. A broad ion beam hits the back of a scanning probe microscope (SPM) cantilever with incorporated apertures. The high resolution imaging capabilities of the SPM allows the non destructive location of device areas and the alignment of the cantilever and thus collimated ion beam spot to the desired implant locations. In this work, this technique is explored, applied and pushed forward to meet necessary precision requirements. The alignment of the ion beam to surface features, which are sensitive to ion impacts and thus act as detectors, is demonstrated. The technique is also used to create NV center arrays in diamond substrates. Further, single ion impacts into silicon device structures are detected which enables deliberate single ion doping

Formation of advanced gate stacks and their application to nano structure devices

Ph.DDOCTOR OF PHILOSOPH

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Dependable Embedded Systems

This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from today’s points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability challenges across different levels starting from the physical level all the way to the system level (cross-layer approaches). The book aims at demonstrating how new hardware/software co-design solution can be proposed to ef-fectively mitigate reliability degradation such as transistor aging, processor variation, temperature effects, soft errors, etc. Provides readers with latest insights into novel, cross-layer methods and models with respect to dependability of embedded systems; Describes cross-layer approaches that can leverage reliability through techniques that are pro-actively designed with respect to techniques at other layers; Explains run-time adaptation and concepts/means of self-organization, in order to achieve error resiliency in complex, future many core systems