Binary Weighted DAC with 2-ξ Resistor Ratio

In this paper we present a new digital analog converter (DAC) design, based on the binary weighted resistor network. The proposed design ensures high conversion accuracy using low precision resistors with ±1% ±2%, ±5%, ±10% and ±20% resistor tolerance. High accuracy is achieved due to better coverage of the analog domain of the transfer characteristic. In binary weighted converters the imprecision of resistors introduces positive and negative differential nonlinearities (DNL). Positive DNL causes gap in the analog domain of the transfer characteristic and negative DNL causes non-monotonicity. In the proposed solution we change the resistor ratio of the two consecutive DAC branches from 2 to 2-ξ, where ξ is small positive number. With this change, we intentionally introduce an additional negative DNL in order to entirely avoid the positive gap. Simulation results confirm that even with resistors tolerance of up to ±10%, we can achieve a converter with maximal gap in the transfer characteristic less than or around one LSB

Robust Design With Increasing Device Variability In Sub-Micron Cmos And Beyond: A Bottom-Up Framework

My Ph.D. research develops a tiered systematic framework for designing process-independent and variability-tolerant integrated circuits. This bottom-up approach starts from designing self-compensated circuits as accurate building blocks, and moves up to sub-systems with negative feedback loop and full system-level calibration. a. Design methodology for self-compensated circuits My collaborators and I proposed a novel design methodology that offers designers intuitive insights to create new topologies that are self-compensated and intrinsically process-independent without external reference. It is the first systematic approaches to create "correct-by-design" low variation circuits, and can scale beyond sub-micron CMOS nodes and extend to emerging non-silicon nano-devices. We demonstrated this methodology with an addition-based current source in both 180nm and 90nm CMOS that has 2.5x improved process variation and 6.7x improved temperature sensitivity, and a GHz ring oscillator (RO) in 90nm CMOS with 65% reduction in frequency variation and 85ppm/oC temperature sensitivity. Compared to previous designs, our RO exhibits the lowest temperature sensitivity and process variation, while consuming the least amount of power in the GHz range. Another self-compensated low noise amplifiers (LNA) we designed also exhibits 3.5x improvement in both process and temperature variation and enhanced supply voltage regulation. As part of the efforts to improve the accuracy of the building blocks, I also demonstrated experimentally that due to "diversification effect", the upper bound of circuit accuracy can be better than the minimum tolerance of on-chip devices (MOSFET, R, C, and L), which allows circuit designers to achieve better accuracy with less chip area and power consumption. b. Negative feedback loop based sub-system I explored the feasibility of using high-accuracy DC blocks as low-variation "rulers-on-chip" to regulate high-speed high-variation blocks (e.g. GHz oscillators). In this way, the trade-off between speed (which can be translated to power) and variation can be effectively de-coupled. I demonstrated this proposed structure in an integrated GHz ring oscillators that achieve 2.6% frequency accuracy and 5x improved temperature sensitivity in 90nm CMOS. c. Power-efficient system-level calibration To enable full system-level calibration and further reduce power consumption in active feedback loops, I implemented a successive-approximation-based calibration scheme in a tunable GHz VCO for low power impulse radio in 65nm CMOS. Events such as power-up and temperature drifts are monitored by the circuits and used to trigger the need-based frequency calibration. With my proposed scheme and circuitry, the calibration can be performed under 135pJ and the oscillator can operate between 0.8 and 2GHz at merely 40[MICRO SIGN]W, which is ideal for extremely power-and-cost constraint applications such as implantable biomedical device and wireless sensor networks

CMOS SPAD-based image sensor for single photon counting and time of flight imaging

The facility to capture the arrival of a single photon, is the fundamental limit to the detection of quantised electromagnetic radiation. An image sensor capable of capturing a picture with this ultimate optical and temporal precision is the pinnacle of photo-sensing. The creation of high spatial resolution, single photon sensitive, and time-resolved image sensors in complementary metal oxide semiconductor (CMOS) technology offers numerous benefits in a wide field of applications. These CMOS devices will be suitable to replace high sensitivity charge-coupled device (CCD) technology (electron-multiplied or electron bombarded) with significantly lower cost and comparable performance in low light or high speed scenarios. For example, with temporal resolution in the order of nano and picoseconds, detailed three-dimensional (3D) pictures can be formed by measuring the time of flight (TOF) of a light pulse. High frame rate imaging of single photons can yield new capabilities in super-resolution microscopy. Also, the imaging of quantum effects such as the entanglement of photons may be realised. The goal of this research project is the development of such an image sensor by exploiting single photon avalanche diodes (SPAD) in advanced imaging-specific 130nm front side illuminated (FSI) CMOS technology. SPADs have three key combined advantages over other imaging technologies: single photon sensitivity, picosecond temporal resolution and the facility to be integrated in standard CMOS technology. Analogue techniques are employed to create an efficient and compact imager that is scalable to mega-pixel arrays. A SPAD-based image sensor is described with 320 by 240 pixels at a pitch of 8μm and an optical efficiency or fill-factor of 26.8%. Each pixel comprises a SPAD with a hybrid analogue counting and memory circuit that makes novel use of a low-power charge transfer amplifier. Global shutter single photon counting images are captured. These exhibit photon shot noise limited statistics with unprecedented low input-referred noise at an equivalent of 0.06 electrons. The CMOS image sensor (CIS) trends of shrinking pixels, increasing array sizes, decreasing read noise, fast readout and oversampled image formation are projected towards the formation of binary single photon imagers or quanta image sensors (QIS). In a binary digital image capture mode, the image sensor offers a look-ahead to the properties and performance of future QISs with 20,000 binary frames per second readout with a bit error rate of 1.7 x 10-3. The bit density, or cumulative binary intensity, against exposure performance of this image sensor is in the shape of the famous Hurter and Driffield densitometry curves of photographic film. Oversampled time-gated binary image capture is demonstrated, capturing 3D TOF images with 3.8cm precision in a 60cm range

Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters

In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and resolution requirements. This is due to the one core single bit quantizer, lack of residue amplification, and large digital domain processing allowing for easy process scaling. This work examines the traditional binary capacitive SAR ADC time and statistical information and proposes new structures that optimize ADC performance. The Ternary SAR (TSAR) uses the quantizer delay information to enhance accuracy, speed and power consumption of the overall SAR while providing multi-level redundancy. The early reset merged capacitor switching SAR (EMCS) identifies lost information in the SAR subtraction and optimizes a full binary quanitzer structure for a Ternary MCS DAC. Residue Shaping is demonstrated in SAR and pipeline configurations to allow for an extra bit of signal to noise quantization ratio (SQNR) due to multi-level redundancy. The feedback initialized ternary SAR (FITSAR) is proposed which splits a TSAR into separate binary and ternary sub-ADC structures for speed and power benefits with an inter-stage encoding that not only maintains residue shaping across the binary SAR, but allows for nearly optimally minimal energy consumption for capacitive ternary DACs. Finally, the ternary SAR ideas are applied to R2R DACs to reduce power consumption. These ideas are tested both in simulation and with prototype results

Precision rail-to-rail input-output operational amplifier using laser-trimmable poly-silicon resistors in standard cmos process

Motivation -- Objective -- Input offset voltage trimming methods for operational amplifiers -- Rail-to-rail input/output amplifiers -- Organization of the dissertation -- Design of a precision CMOS operational amplifier and PTAT bias generator -- Precision analog circuit design considerations -- CMOS rail-to-rail I/O operational amplifier design -- Effect of load resistor trimming on offset voltage -- CMOS PTAT bias circuit design -- IC layout implementation -- Simulation results and experimental verification -- Conclusion and future work

Photo-magnonics in two-dimensional antidot lattices

Wesentlicher Gegenstand der vorliegenden (kumulativen) Dissertation ist die ausschließlich optische Erzeugung und Detektion sowie gezielte Manipulation magnetischer Anregungen, sogenannter Spinwellen oder Magnonen. Insbesondere werden die Mechanismen und Prozesse diskutiert, die zur Beobachtung wohldefinierter Spinwellenmoden in dünnen magnetischen Filmen führen, nachdem ein intensiver, ultrakurzer Laserpuls absorbiert wurde. Eine langreichweitig geordnete, periodische Strukturierung der magnetischen Filme (in diesem Fall mit Löchern) ist sodann gleichbedeutend mit der Schaffung magnetischer Metamaterialien (d.h. magnonischer Kristalle). Abhängig von Wirtsmaterial (Nickel oder Kobalt-Eisen-Bor) und strukturellen Eigenschaften der Lochgitter (Periodizität, strukturelle Einheit) ist die Erzeugung oder Unterdrückung bestimmter magnetischer Moden möglich. So führt die vergleichsweise große intrinsische magnetische Dämpfung in Nickel zur Ausbildung lokalisierter Spinwellen, während wegen der geringen Dämpfung in Kobalt-Eisen-Bor ausgedehnte Blochwellen beobachtet werden. Deren Wellenlänge ist zudem einstellbar mittels der Periodizität des Metamaterials und wird anhand numerischer Berechnungen der (magnonischen) Bandstrukturen nachvollzogen. Zuletzt werden auf Basis dieser Ergebnisse mögliche Anwendungen magnonischer Kristalle diskutiert. Hierbei liegt ein Schwerpunkt auf anisotropen Lochgittern und deren Perspektive als Spinwellenfilter

Cutting Edge Nanotechnology

The main purpose of this book is to describe important issues in various types of devices ranging from conventional transistors (opening chapters of the book) to molecular electronic devices whose fabrication and operation is discussed in the last few chapters of the book. As such, this book can serve as a guide for identifications of important areas of research in micro, nano and molecular electronics. We deeply acknowledge valuable contributions that each of the authors made in writing these excellent chapters