Three-Dimensional MOS Process Development

A novel MOS technology for three-dimensional integration of electronic circuits on silicon substrates was developed. Selective epitaxial growth and epitaxial lateral overgrowth of monocrystalline silicon over oxidized silicon were employed to create locally restricted silicon-on-insulator device islands. Thin gate oxides were discovered to deteriorate in ambients typically used for selective epitaxial growth. Conditions of general applicability to silicon epitaxy systems were determined under which this deterioration was greatly reduced. Selective epitaxial growth needed to be carried out at low temperatures. However, crystalline defects increase as deposition temperatures are decreased. An exact dependence between the residual moisture content in epitaxial growth ambients, deposition pressure, and deposition temperature was determined which is also generally applicable to silicon epitaxy systems. The dependences of growth rates and growth rate uniformity on loading, temperature, flow rates, gas composition, and masking oxide thickness were investigated for a pancake type epitaxy reactor. A conceptual model was discussed attempting to describe the effects peculiar to selective epitaxial growth. The newly developed processing steps were assembled to fabricate three dimensional silicon-on-insulator capacitors. These capacitors were electrically evaluated. Surface state densities were in the order of 1O11cm-2 eV-1 and therefore within the range of applicability for a practical CMOS process. Oxidized polysilicon gates were overgrown with silicon by epitaxial lateral overgrowth. The epitaxial silicon was planarized and source and drain regions were formed above the polysilicon gates in Silicon-on-insulator material. The modulation of the source-drain current by bias changes of the buried gate was demonstrated

Study of a New Silicon Epitaxy Technique: Confined Lateral Selective Epitaxial Growth

This work describes a significant new advance in the technique of silicon selective epitaxy called Confined Lateral Selective Epitaxial Growth (CLSEG). CLSEG is a method for forming thin films of single crystal silicon on top of an insulating layer or film. Such thin films are generically termed Silicon-On- Insulator (SOI), and1 allow dielectric isolation of integrated circuit elements, making them more efficient (faster with lower power), more resistant to radiation, and smaller than conventional integrated circuits, ionizing radiation than conventional integrated circuits. CLSEG offers advantages over current methods of achieving SOI by being easily manufactured, inherently reproducible, and having greater design flexibility. CLSEG is also adaptable to vertical stacking of devices in a circuit, in what is called three-dimensional integration, for even greater reductions in area. In addition, CLSEG can be used for a wide variety of sensor and micromachining application. This thesis describes the design and development of CLSEG, and compares it to the current state of the art in the fields of SOI and Selective Epitaxial Growth (SEG). CLSEG is accomplished by growing silicon selective epitaxy within a cavity; which is formed of dielectric materials upon a silicon substrate. The resulting SOI film can be made as thin as 0.1 micron, and tens of microns wide, with an unlimited length. In particular, there is now strong evidence that surface diffusivity of silicon adatoms on the dielectric masking layers is a significant contributor to the transport of silicon to the growth surface during SE G. CLSEG silicon material quality is evaluated by fabricating a variety of semiconductor devices in CLSEG films. These devices demonstrate the applicability of CLSEG to integrated circuits, and provide a basis of comparison between CLSEG-grown silicon and device-quality substrate silicon. Then, CLSEG is used to fabricate an advanced device structure, verifying the value and significance of this new epitaxy technique. In the final two chapters, CLSEG is evaluated as a technology, and compared to the current state of the art. Then, a method is presented Tor forming CLSEG with only one photolithography step, and a process is described for making a SOI film across an entire silicon wafer using CLSEG. These techniques may indicate the feasibility of using CLSEG for three dimensional integration of microelectronics. It is hoped that this work will establish a firm basis for further study of this interesting and valuable new technology

Three Dimensional Integration (3DI) of semiconductor circuit layers: new devices and fabrication process

The device density of Integrated Circuits (ICs) manufactured by current VLSI technology is reaching it\u27s theoretical limit. Nevertheless, the demand for integration of more devices per chip is growing. To accommodate this need three main possibilities can be explored: Wafer Scale Integration (WSI), Ultra Large Scale Integration (ULSI), and Three Dimensional Integration (3DI). A brief review of these techniques along with their comparative advantages and disadvantages is presented. It has been concluded that 3DI technology is superior to others. Therefore, an attempt is made to develop a viable fabrication process for this technology. This is done by first reviewing the current technologies that are utilized for fabrication of Integrated Circuits (ICs) and their compatibility with 3DI stringent requirements.;Based on this review, a set of fabrication procedure for realization of 3DI technology, are presented in chapter 3. In Chapter 1 the compatibility of the currently used devices, such as BJTs and FETS, with 3DI technology is examined. Moreover, a new active device is developed for 3DI technology to replace BJTs and FETs in circuits. This new device is more compatible to the constrains of 3DI technology. Chapter 2 is devoted to solving the overall problems of 3DI circuits. The problem of heat and power dispassion and signal coupling (Cross-Talk) between the layers are reviewed, and an inter-layer shield is proposed to overcome these problems. The effectiveness of such a thin shield is considered theoretically. In Chapter 3 a fabrication process for 3DI technology is proposed. This is done after a short analysis of previous attempts in developing 3DI technologies.;Chapter 4 focuses on analog extension of 3DI technology. Moreover, in this chapter microwave 3DI circuits or 3DI MMIC is investigated. Practical considerations in choice of material for the proposed device is the subject of study in Chapter 5. Low temperature ohmic contact and utilization of metal-silicides for the proposed device are considered in this chapter. Finally in Chapter 6 various computer verifications for this work is presented, and in Chapter 7 experimental results to support this work is included

Journal of Telecommunications and Information Technology, 2001, nr 1

kwartalni

Local Epitaxial Overgrowth for Stacked Complementary MOS Transistor Pairs

A three-dimensional silicon processing technology for CMOS circuits was developed and characterized. The first fully depleted SOI devices with individually biasable gates on both sides of the silicon film were realized. A vertically stacked CMOS Inverter built by lateral overgrowth was reported for the first time. Nucleation-free epitaxial lateral overgrowth of silicon over thin oxides was developed for both a pancake and a barrel-type epitaxy reactor: This process was optimized to limit damage to gate oxides and minimize dopant diffusion within the Substrate. Autodoping from impurities of the MOS transistors built in the substrate was greatly reduced. A planarisation technique was developed to reduce the silicon film thickness from 13μm to below 0.5μm for full depletion. Chemo-mechanical polishing was modified to yield an automatic etch stop with the corresponding control and uniformity of the silicon film. The resulting wafer topography is more planar than in a conventional substrate CMOS process. PMOS transistors which match the current drive of bulk NM0S devices of equal geometry were characterized, despite the three-times lower hole mobility. Devices realized in the substrate, at the bottom and on top of the SOI film were essentially indistinguishable from bulk devices. A novel device with two insulated gates controlling the same channel was characterized. Inverters were realized both as joint-gate configuration and with symmetric performance of n- and p-channel. These circuits were realized in the area of a single NMOS transistor

The Journal of Microelectronic Research

https://scholarworks.rit.edu/meec_archive/1013/thumbnail.jp

A study of the device characteristics of a novel body-contact SOI structure.

Lau Wai Kwok.Thesis (M.Phil.)--Chinese University of Hong Kong, 1996.Includes bibliographical references.Acknowledgement --- p.ivAbstract --- p.vChapter Chapter 1 --- Introduction --- p.1-1Chapter 1.1 --- Perspective --- p.1-1Chapter 1.2 --- MEDICI - The Simulation Package --- p.1 -2Chapter 1.3 --- Overview --- p.1-3Chapter Chapter 2 --- The Emergence of SOI Devices --- p.2-1Chapter 2.1 --- Introduction --- p.2-1Chapter 2.2 --- Advantages of SOI Devices --- p.2-1Chapter 2.2.1 --- Reliability Improvement --- p.2-2Chapter 2.2.2 --- Total Isolation --- p.2-3Chapter 2.2.3 --- Improved Junction Structure --- p.2-4Chapter 2.2.4 --- Integrated Device Structure --- p.2-5Chapter 2.3 --- Categories of SOI Devices --- p.2-6Chapter 2.3.1 --- Thick Film SOI Devices --- p.2-7Chapter 2.3.2 --- Thin Film SOI Devices --- p.2-8Chapter 2.3.3 --- Medium Film SOI Devices --- p.2-8Chapter 2.4 --- Drawbacks of SOI Devices --- p.2-9Chapter 2.4.1 --- Floating Body Effects --- p.2-9Chapter 2.4.2 --- Parasitic Bipolar Effects --- p.2-11Chapter 2.4.3 --- Cost --- p.2-15Chapter 2.5 --- Manufacturing Methods --- p.2-16Chapter 2.5.1 --- Epitaxy-Based Method --- p.2-16Chapter 2.5.2 --- Recrystallization-Based Method --- p.2-18Chapter 2.5.3 --- Wafer Bonding Based Method --- p.2-19Chapter 2.5.4 --- Oxidation Based Method --- p.2-20Chapter 2.5.5 --- Implantation Based Method --- p.2-22Chapter 2.6 --- Future Trend --- p.2-22Chapter 2.7 --- The Quest for Silicon-On-Nitride Structure --- p.2-23Chapter Chapter 3 --- Description of Body-Contact SOI Structure --- p.3-1Chapter 3.1 --- Introduction --- p.3-1Chapter 3.2 --- Current Status of Body-Contact SOI Structure --- p.3-1Chapter 3.3 --- The Body-Contact SOI Structure to be studied --- p.3-4Chapter 3.4 --- Impact on Device Fabrication --- p.3-7Chapter 3.4.1 --- Fabrication of Conventional Bulk CMOS --- p.3-7Chapter 3.4.2 --- Fabrication of Conventional SOI CMOS --- p.3-8Chapter 3.4.3 --- Fabrication of BC SOI CMOS --- p.3-10Chapter Chapter 4 --- Device Simulations --- p.4-1Chapter 4.1 --- Introduction --- p.4-1Chapter 4.2 --- MEDICI --- p.4-1Chapter 4.2.1 --- Basic Equations --- p.4-2Chapter 4.2.2 --- Solution Methods --- p.4-3Chapter 4.2.3 --- Initial Guess --- p.4-6Chapter 4.2.4 --- Grid Allocations --- p.4-7Chapter 4.2.5 --- Source File --- p.4-8Chapter 4.3 --- Structures for Simulations --- p.4-9Chapter 4.3.1 --- l.2μm NMOS Bulk (LDD) --- p.4-9Chapter 4.3.2 --- 1.2μm SOI(O) NMOS 1000/3500 NBC --- p.4-11Chapter 4.3.3 --- 1.2μm SOI(N) NMOS 1000/3500 NBC --- p.4-12Chapter 4.3.4 --- 1.2μm SOI(O) NMOS 1000/3500 WBC --- p.4-13Chapter 4.3.5 --- 1.2μm SOI(N) NMOS 1000/3500 WBC --- p.4-14Chapter 4.4 --- Summary --- p.4-14Chapter Chapter 5 --- Simulation Results --- p.5-1Chapter 5.1 --- Introduction --- p.5-1Chapter 5.2 --- Comparisons of Different Structures --- p.5-1Chapter 5.2.1 --- Impurity Profiles of Structures --- p.5-2Chapter 5.2.2 --- Body Effect --- p.5-10Chapter 5.2.3 --- Breakdown Voltage and Transistor Current Driving --- p.5-16Chapter 5.2.4 --- Transconductance and Mobility --- p.5-20Chapter 5.2.5 --- Subthreshold Swing --- p.5-23Chapter 5.3 --- Dependence on Key Structure Parameters --- p.5-29Chapter 5.3.1 --- Dependence on Insulator Thickness --- p.5-29Chapter 5.3.2 --- Dependence on Silicon Overlayer Thickness --- p.5-34Chapter 5.3.3 --- Dependence on Size of Body-Contact --- p.5-37Chapter 5.4 --- Summary --- p.5-40Chapter Chapter 6 --- Reduction of Latch-up Susceptibility --- p.6-1Chapter 6.1 --- Introduction --- p.6-1Chapter 6.2 --- Construction of a p-channel MOS Transistor --- p.6-2Chapter 6.2.1 --- Threshold Voltage and Body Effect --- p.6-3Chapter 6.2.2 --- I-V Characteristics --- p.6-3Chapter 6.2.3 --- Transconductance --- p.6-5Chapter 6.2.4 --- Subthreshold Swing --- p.6-5Chapter 6.3 --- Mechanism of Latch-up in CMOS --- p.6-6Chapter 6.4 --- Construction of a CMOS Invertor for Simulation --- p.6-10Chapter 6.5 --- Latch-up Susceptibility Dependence --- p.6-16Chapter 6.5.1 --- Dependence on Insulator Thickness --- p.6-16Chapter 6.5.2 --- Dependence on N-well Depth --- p.6-19Chapter 6.5.3 --- Dependence on Transistor Separation --- p.6-22Chapter 6.5.4 --- Dependence on Size of Body-Contact --- p.6-25Chapter 6.6 --- Summary --- p.6-28Chapter Chapter 7 --- Conclusions --- p.7-1Chapter 7.1 --- Summary --- p.7-1Chapter 7.2 --- Recommendation --- p.7-3ReferenceAppendix

On-a-chip microdischarge thruster arrays inspired by photonic device technology for plasma television

This study shows that the practical scaling of a hollow cathode thruster device to MEMS level should be possible albeit with significant divergence from traditional design. The main divergence is the need to operate at discharge pressures between 1-3bar to maintain emitter diameter pressure products of similar values to conventional hollow cathode devices. Without operating at these pressures emitter cavity dimensions become prohibitively large for maintenance of the hollow cathode effect and without which discharge voltage would be in the hundreds of volts as with conventional microdischarge devices. In addition this requires sufficiently constrictive orifice diameters in the 10µm – 50µm range for single cathodes or <5µm larger arrays. Operation at this pressure results in very small Debye lengths (4 -5.2pm) and leads to large reductions in effective work function (0.3 – 0.43eV) via the Schottky effect. Consequently, simple work function lowering compounds such as lanthanum hexaboride (LaB6) can be used to reduce operating temperature without the significant manufacturing complexity of producing porous impregnated thermionic emitters as with macro scale hollow cathodes, while still operating <1200°C at the emitter surface. The literature shows that LaB6 can be deposited using a variety of standard microfabrication techniques

Flash Lamp Annealed LTPS TFTs with ITO Bottom-Gate Structures

As displays continue to increase in resolution and refresh rate, new materials for thin film transistors (TFTs) are required. Low temperature polycrystalline silicon (LTPS) formed by excimer laser annealing (ELA) has been very successful and has been implemented in small displays, but cost and scalability issues prevent it from entering larger display products. Currently LPTS TFTs are top-gate structures due to manufacturing challenges associated with crystallizing thin film silicon when a thermally conductive gate is under portions and insulating glass under others. Bottom-gate devices offer the benefit of higher breakdown voltage, better dielectric-semiconductor interface quality, and direct access to the back-channel region for interface trap passivation. The ability to fabricate bottom-gate devices would allow for different integration and design schemes and is a prerequisite for double gate structures. Flash lamp annealed (FLA) LTPS is an attractive method to expand the size of displays that use high mobility TFTs due to its scalability and parallel production nature. In this work bottom-gate LTPS TFTs were fabricated via FLA with indium tin oxide (ITO), a transparent conductive oxide, used as the gate electrode. A p-channel TFT with 4 µm channel length crystallized with a FLA energy of 4.4 J/cm2 for 250 µs demonstrated a low-field mobility of 190 cm2/(Vs), a subthreshold slope of 325 mV/dec, on/off state ratio of seven orders of magnitude, and a threshold voltage of -5.4 V. A dielectric failure mechanism was identified that compromised the transistor operation under high drain bias and an alternative dopant introduction techniques were proposed to mitigate this issue. An effect due to the transduction of optical energy from the field to thermal energy under the channel via the gate was observed. Details of the FLA crystallization process, device fabrication, and electrical characteristics will be presented