A 5.3mW, 2.4GHz ESD protected Low-Noise Amplifier in a 0.13μm RFCMOS technology

An Electrostatic Discharge (ESD) protected Low- Noise Amplifier (LNA) for the 2.4 GHz ISM band designed in a 0.13 mum standard RFCMOS technology is presented. The amplifier, including packaging effects, achieves 16.8 dB power gain, reflexion coefficients S 11 , S 22 < -30 dB over the 2.4 GHz ISM band, a peak noise figure of 1.8 dB, and an IIP 3 of 1 dBm, while drawing less than 4.5 mA dc biasing current from the 1.2 V power supply. Further, the LNA withstands a Human Body Model (HBM) ESD stress up to plusmn2.0 kV, by means of the additional custom protection circuitry.Comisión Interministerial de Ciencia y Tecnología TIC2003-02355Ministerio de Educación y Ciencia TEC2006-0302

A low-power RF front-end for 2.5 GHz receivers

© 2008 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a low power and low cost front end for a direct conversion 2.5 GHz ISM band receiver composed of a 16 kV HBM ESD protected LNA, differential Gilbert-cell mixers, and high-pass filters for DC offset cancellation. The whole front-end is implemented in a 2P6M 0.18 µm RFCMOS process. It exhibits a voltage gain of 24dB and a SSB noise figure of 8.4dB which make it suitable for most of the 2.5 GHz wireless short-range communication transceivers. The achieved power consumption is only 1.06mW from a 1.2V power supply.Peer ReviewedPostprint (published version

Dynamic input match correction in R.F. low noise amplifiers

An R.F. circuit that recognizes its faults, and then corrects its performance in real-time has been the holy-grail of RFIC design. This work presents, for the first time, a complete architecture and successful implementation of such a circuit. It is the first step towards the grand vision of fault-free, package independent, integrated R.F. Front End circuitry. The performance of R.F. front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input. These inductances have wide tolerances and are difficult to co-design for. A novel methodology, which overcomes current obstacles plaguing such an objective, is proposed wherein the affected performance metric of the circuit is quantified, and the appropriate design parameter is modified in real-time, thus enabling self-correction. This proof of concept is demonstrated by designing a cascode LNA and the complete self-correction circuit in IBM 0.25 µm CMOS RF process. The self-correction circuitry ascertains the input match frequency of the circuit by measuring its performance and determines the frequency interval by which it needs to be shifted to restore it to the desired value. It then feeds back a digital word to the LNA which adaptively corrects its input-match. It offers the additional flexibility of using different packages for the front-end since it renders the circuitry independent of package parasitics, by re-calibrating the input match on-the-fly. The circuitry presented in this work offers the advantages of low power, robustness, absence of DSP cores or processors, reduction in design cycle times, guaranteed optimal performance under varying conditions and fast correction times (less than 30 µs)

CMOS RF low noise amplifier with high ESD immunity.

Tang Siu Kei.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 107-111).Abstracts in English and Chinese.Acknowledgements --- p.iiAbstract --- p.iiiList of Figures --- p.xiList of Tables --- p.xviChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Overview of Electrostatic Discharge --- p.1Chapter 1.1.1 --- Classification of Electrostatic Discharge Models --- p.1Chapter 1.2 --- Electrostatic Discharge in CMOS RF Circuits --- p.4Chapter 1.3 --- Research Goal and Contribution --- p.6Chapter 1.4 --- Thesis Outline --- p.6Chapter Chapter 2 --- Performance Parameters of Amplifier --- p.8Chapter 2.1 --- Amplifier Gain --- p.8Chapter 2.2 --- Noise Factor --- p.9Chapter 2.3 --- Linearity --- p.11Chapter 2.3.1 --- 1-dB Compression Point --- p.13Chapter 2.3.2 --- Third-Order Intercept Point --- p.14Chapter 2.4 --- Return Loss --- p.16Chapter 2.5 --- Power Consumption --- p.18Chapter 2.6 --- HBM ESD Withstand Voltage --- p.19Chapter Chapter 3 --- ESD Protection Methodology for Low Noise Amplifier --- p.21Chapter 3.1 --- Dual-Diode Circuitry --- p.22Chapter 3.1.1 --- Working Principle --- p.22Chapter 3.1.2 --- Drawbacks --- p.24Chapter 3.2 --- Shunt-Inductor Method --- p.25Chapter 3.2.1 --- Working Principle --- p.25Chapter 3.2.2 --- Drawbacks --- p.27Chapter 3.3 --- Common-Gate Input Stage Method --- p.28Chapter 3.3.1 --- Built-in ESD Protecting Mechanism --- p.29Chapter 3.3.2 --- Competitiveness --- p.31Chapter Chapter 4 --- Design Theory of Low Noise Amplifier --- p.32Chapter 4.1 --- Small-Signal Modeling --- p.33Chapter 4.2 --- Method of Input Termination --- p.33Chapter 4.2.1 --- Resistive Termination --- p.34Chapter 4.2.2 --- Shunt-Series Feedback --- p.34Chapter 4.2.3 --- l/gm Termination --- p.35Chapter 4.2.4 --- Inductive Source Degeneration --- p.36Chapter 4.3 --- Method of Gain Enhancement --- p.38Chapter 4.3.1 --- Tuned Amplifier --- p.38Chapter 4.3.2 --- Multistage Amplifier --- p.40Chapter 4.4 --- Improvement of Reverse Isolation --- p.41Chapter 4.4.1 --- Common-Gate Amplifier --- p.41Chapter 4.4.2 --- Cascoded Amplifier --- p.42Chapter Chapter 5 --- Noise Analysis of Low Noise Amplifier --- p.44Chapter 5.1 --- Noise Sources of MOS Transistor --- p.44Chapter 5.2 --- Noise Calculation using Noisy Two-Port Network --- p.46Chapter 5.3 --- Noise Calculation using Small-Signal Model --- p.49Chapter 5.3.1 --- Low Noise Amplifier with Inductive Source Degeneration --- p.49Chapter 5.3.2 --- Common-Gate Low Noise Amplifier --- p.52Chapter Chapter 6 --- Design of an ESD-protected CMOS Low Noise Amplifier --- p.54Chapter 6.1 --- Design of DC Biasing Circuitry --- p.55Chapter 6.2 --- Design of Two-Stage Architecture --- p.57Chapter 8.3.1 --- Design of Common-Gate Input Stage --- p.57Chapter 8.3.2 --- Design of Second-Stage Amplifier --- p.59Chapter 6.3 --- Stability Consideration --- p.61Chapter 6.4 --- Design of Matching Networks --- p.62Chapter 6.4.1 --- Design of Inter-Stage Matching Network --- p.64Chapter 6.4.2 --- Design of Input and Output Matching Networks --- p.67Chapter Chapter 7 --- Layout Considerations --- p.70Chapter 7.1 --- MOS Transistor --- p.70Chapter 7.2 --- Capacitor --- p.72Chapter 7.3 --- Spiral Inductor --- p.74Chapter 7.4 --- Layout of the Proposed Low Noise Amplifier --- p.76Chapter 7.5 --- Layout of the Common-Source Low Noise Amplifier --- p.79Chapter 7.6 --- Comparison between Schematic and Post-Layout Simulation Results --- p.81Chapter Chapter 8 --- Measurement Results --- p.82Chapter 8.1 --- Experimental Setup --- p.82Chapter 8.1.1 --- Testing Circuit Board --- p.83Chapter 8.1.2 --- Experimental Setup for s-parameter --- p.84Chapter 8.1.3 --- Experimental Setup for Noise Figure --- p.84Chapter 8.1.4 --- Experimental Setup for 1-dB Compression Point --- p.85Chapter 8.1.5 --- Experimental Setup for Third-Order Intercept Point --- p.86Chapter 8.1.6 --- Setup for HBM ESD Test --- p.87Chapter 8.2 --- Measurement Results of the Proposed Low Noise Amplifier --- p.89Chapter 8.2.1 --- S-parameter Measurement --- p.90Chapter 8.2.2 --- Noise Figure Measurement --- p.91Chapter 8.2.3 --- Measurement of 1-dB Compression Point --- p.92Chapter 8.2.4 --- Measurement of Third-Order Intercept Point --- p.93Chapter 8.2.5 --- HBM ESD Test --- p.94Chapter 8.2.6 --- Summary of Measurement Results --- p.95Chapter 8.3 --- Measurement Results of the Common-Source Low Noise Amplifier --- p.96Chapter 8.3.1 --- s-parameter Measurement --- p.97Chapter 8.3.2 --- Noise Figure Measurement --- p.98Chapter 8.3.3 --- Measurement of 1-dB Compression Point --- p.99Chapter 8.3.4 --- Measurement of Third-Order Intercept Point --- p.100Chapter 8.3.5 --- HBM ESD Test --- p.101Chapter 8.3.6 --- Summary of Measurement Results --- p.102Chapter 8.4 --- Performance Comparison between Different Low Noise Amplifier Designs --- p.103Chapter Chapter 9 --- Conclusion and Future Work --- p.105Chapter 9.1 --- Conclusion --- p.105Chapter 9.2 --- Future Work --- p.106References --- p.107Author's Publications --- p.11

Study Of Esd Effects On Rf Power Amplifiers

Today, ESD is a major consideration in the design and manufacture of ICs. ESD problems are increasing in the electronics industry because of the increasing trend toward higher speed and smaller device sizes. There is growing interest in knowing the effects of ESD protection circuit on the performance of semiconductor integrated circuits (ICs) because of the impact it has on core RF circuit performance. This study investigated the impact of ESD protection circuit on RF Power amplifiers. Even though ESD protection for digital circuits has been known for a while, RF-ESD is a challenge. From a thorough literature search on prior art ESD protection circuits, Silicon controlled rectifier was found to be most effective and reliable ESD protection for power amplifier circuit. A SCR based ESD protection was used to protect the power amplifier and a model was developed to gain better understanding of ESD protected power amplifiers. Simulated results were compared and contrasted against theoretically derived equations. A 5.2GHz fully ESD protected Class AB power amplifier was designed and simulated using TSMC 0.18 um technology. Further, the ESD protection circuit was added to a cascoded Class-E power amplifier operating at 5.2 GHz. ADS simulation results were used to analyze the PA’s RF performance degradation. Various optimization techniques were used to improve the RF circuit performance

Design methodologies for built-in testing of integrated RF transceivers with the on-chip loopback technique

Advances toward increased integration and complexity of radio frequency (RF) andmixed-signal integrated circuits reduce the effectiveness of contemporary testmethodologies and result in a rising cost of testing. The focus in this research is on thecircuit-level implementation of alternative test strategies for integrated wirelesstransceivers with the aim to lower test cost by eliminating the need for expensive RFequipment during production testing.The first circuit proposed in this thesis closes the signal path between the transmitterand receiver sections of integrated transceivers in test mode for bit error rate analysis atlow frequencies. Furthermore, the output power of this on-chip loopback block wasmade variable with the goal to allow gain and 1-dB compression point determination forthe RF front-end circuits with on-chip power detectors. The loopback block is intendedfor transceivers operating in the 1.9-2.4GHz range and it can compensate for transmitterreceiveroffset frequency differences from 40MHz to 200MHz. The measuredattenuation range of the 0.052mm2 loopback circuit in 0.13µm CMOS technology was 26-41dB with continuous control, but post-layout simulation results indicate that theattenuation range can be reduced to 11-27dB via optimizations.Another circuit presented in this thesis is a current generator for built-in testing ofimpedance-matched RF front-end circuits with current injection. Since this circuit hashigh output impedance (>1k up to 2.4GHz), it does not influence the input matchingnetwork of the low-noise amplifier (LNA) under test. A major advantage of the currentinjection method over the typical voltage-mode approach is that the built-in test canexpose fabrication defects in components of the matching network in addition to on-chipdevices. The current generator was employed together with two power detectors in arealization of a built-in test for a LNA with 14% layout area overhead in 0.13µm CMOStechnology (<1.5% for the 0.002mm2 current generator). The post-layout simulationresults showed that the LNA gain (S21) estimation with the external matching networkwas within 3.5% of the actual gain in the presence of process-voltage-temperaturevariations and power detector imprecision

20W Output Broadband Amplifier with Automatic Gain Control and Thermal Protection

The requirement is to explore concept, design, fabrication and testing of a common source class B, cwrf amplifier by using readily available MOSFET that can withstand a load mismatch at all phase angles with more than a VSWR of 20:1. This amplifier must give an output of more than 20W with 13dB gain in the frequency range of 28 to 46MHz i.e. 37 ± 9MHz. This module will make one of the stages for a multistage cascaded high power cwrf solid state amplifier. The amplifier must be over current and over voltage protected by using external self-regulated dc power supply at the drain. The amplifier MOSFET device is presently to be biased at the gate with a variable dc supply. This arrangement will make it gain controlled. This will be feed backed from the cwrf output so as to make it automatic gain controlled in future. Various techniques of sampling forward and reflected power at the output must also be explored. A thermoswitch at the heat sink of MOSFET is to be added along with necessary circuitry to regulate the operating temperature, thereby protecting the device from overheating

Design of a low noise amplier for a X-band phased array radar system in SiGe BiCMOS technology

A LNA is the first active stage of a radio frequency receiver module, with the prevalent goal of minimizing the noise figure of the whole system. This work presents the design of two narrow-band LNA and a wide-band LNA for phased array radar applications. Silicon-germanium (SiGe) technology is discussed, evaluating its physical characteristics and its potential. The analysis of the low noise ampliers is examined, and the full-custom layout of each discussed circuit is also presentedopenEmbargo per motivi di segretezza e/o di proprietà dei risultati e informazioni di enti esterni o aziende private che hanno partecipato alla realizzazione del lavoro di ricerca relativo alla tes