An LDMOS VHF class-E power amplifier using a high-Q novel variable inductor

In this paper, an lateral diffused metal-oxide-semiconductor-based very high-frequency class-E power amplifier has been investigated theoretically and experimentally. Simulations were verified by amplifier measurements and a record-high class-E output power was obtained at 144 MHz, which is in excellent agreement with simulations. The key of the results is the use of efficient device models, simulation tools, and the invention of a novel high-Q inductor for the output series resonance network. The latter allows for low losses in the output network and, simultaneously, a wide tuning range for maximum output power or maximum efficiency optimization

Fast physical models for Si LDMOS power transistor characterization

A new nonlinear, process-oriented, quasi-two-dimensional (Q2D) model is described for microwave laterally diffused MOS (LDMOS) power transistors. A set of one-dimensional energy transport equations are solved across a two-dimensional cross-section in a “current-driven” form. The model accounts for avalanche breakdown and gate conduction, and accurately predicts DC and microwave characteristics at execution speeds sufficiently fast for circuit simulation applications

Comparative analysis of VDMOS/LDMOS power transistors for RF amplifiers

A comparison between the RF performance of vertical and lateral power MOSFETs is presented. The role of each parasitic parameter in the assessment of the power gain, 1-dB compression point, efficiency, stability, and output matching is evaluated quantitatively using new analytical expressions derived from a ten-element model. This study reveals that the contribution of the parasitic parameter on degradation of performance depends upon the specific technology and generic perceptions of source inductance and feedback capacitance in VDMOS degradation may not always hold. This conclusion is supported by a detailed analysis of three devices of the same power rating from three different commercial vendors. A methodology for optimizing a device technology, specifically for RF performance and power amplifier performance is demonstrated

A breakdown voltage model for implanted resurf p-LDMOS device on n+ buried layer

This paper presents an analytical expression of the breakdown voltage of a high voltage implanted RESURF p-LDMOS device which uses the n+ buried layer as an effective device substrate. In this model, the doping profile of the buried layer is considered and discussed. The implant dose for the drift region to implement the RESURF principle is also described by this model. Results calculated from this model are verified by experimental values

Theory Based on Device Current Clipping to Explain and Predict Performance Including Distortion of Power Amplifiers for Wireless Communication Systems

Power amplifiers are critical components in wireless communication systems that need to have high efficiency, in order to conserve battery life and minimise heat generation, and at the same time low distortion, in order to prevent increase of bit error rate due to constellation errors and adjacent channel interference. This thesis is aimed at meeting a need for greater understanding of distortion generated by power amplifiers of any technology, in order to help designers manage better the trade-off between obtaining high efficiency and low distortion. The theory proposed in this thesis to explain and predict the performance of power amplifiers, including distortion, is based on analysis of clipping of the power amplifier device current, and it is a major extension of previous clipping analyses, that introduces many key definitions and concepts. Distortion and other power amplifier metrics are determined in the form of 3-D surfaces that are plotted against PA class, which is determined by bias voltage, and input signal power level. It is shown that the surface of distortion exhibits very high levels due to clipping in the region where efficiency is high. This area of high distortion is intersected by a valley that is ‘L’-shaped. The 'L'-shaped valley is subject to a rotation that depends on the softness of the cut-off of the power amplifier device transfer characteristic. The distortion surface with rotated 'L'-shaped valley leads to predicted curves for distortion versus input signal power that match published measured curves for power amplifiers even using very simple device models. The distortion versus input signal power curves have types that are independent of technology. In class C, there is a single deep null. In the class AB range, that is divided into three sub-ranges, there may be two deep nulls (sub-range AB(B)), a ledge (sub-range AB(A)) or a shallow null with varying depth (sub-range AB(AB))

Recent Advances in Real-Time Load-Pull Systems

In this paper, some of the latest advances in real-time load-pull technologies will be described. A recently introduced ultralow-loss directional coupler, which has been designed and realized by the authors, provides a number of advantages when used in load-pull test sets. This device has been called the load-pull head. The new ultralow-loss load-pull head can transform any passive precalibrated load-pull system into an easily calibrated and accurate real-time load-pull test set, without losing highreflection- coefficient capabilities. Moreover, if used to realize an active loop, the load-pull head reduces the risks of oscillations and the amount of the loop amplifier output power. As an example application, measurements with a passive real-time load-pull setup of a 30-W laterally diffused MOS (LDMOS) transistor are presented. Furthermore, some advice to bypass the remaining unavoidable losses due to probes and cables is given.We will show, with measurements and with very simple calculations, that the combined use of load-pull heads, a passive tuner, and an active loop not only boosts the available ΓL but also decreases the loop amplifier output power, with a sensible reduction in the overall cost of the syste

An Initial study on The Reliability of Power Semiconductor Devices

An initial literature study combined with some basic comparative simulations has been performed on different electricfield modulation techniques and the subsequent reliability issues are reported for power semiconductor devices. An explanation of the most important power device metrics such as the offstate breakdown (BV) and specific on-resistance (RON) will be given, followed by a short overview of some of the electrostatic techniques (fieldplates, RESURF e.g. [1]) used to suppress peak electric fields. Furthermore it will be addressed that the high current operation of these devices results in shifting electric field peaks (Kirk effect [2], [3]) and as such different avalanche behavior, resulting in (gate oxide) reliability issues unlike those of conventional CMOS

When self-consistency makes a difference

Compound semiconductor power RF and microwave device modeling requires, in many cases, the use of selfconsistent electrothermal equivalent circuits. The slow thermal dynamics and the thermal nonlinearity should be accurately included in the model; otherwise, some response features subtly related to the detailed frequency behavior of the slow thermal dynamics would be inaccurately reproduced or completely distorted. In this contribution we show two examples, concerning current collapse in HBTs and modeling of IMPs in GaN HEMTs. Accurate thermal modeling is proved to be be made compatible with circuit-oriented CAD tools through a proper choice of system-level approximations; in the discussion we exploit a Wiener approach, but of course the strategy should be tailored to the specific problem under consideratio