Carrier Transport in High Mobility InAs Nanowire Junctionless Transistors

Ability to understand and model the performance limits of nanowire transistors is the key to design of next generation devices. Here, we report studies on high-mobility junction-less gate-all-around nanowire field effect transistor with carrier mobility reaching 2000 cm2/V.s at room temperature. Temperature-dependent transport measurements reveal activated transport at low temperatures due to surface donors, while at room temperature the transport shows a diffusive behavior. From the conductivity data, the extracted value of sound velocity in InAs nanowires is found to be an order less than the bulk. This low sound velocity is attributed to the extended crystal defects that ubiquitously appear in these nanowires. Analyzing the temperature-dependent mobility data, we identify the key scattering mechanisms limiting the carrier transport in these nanowires. Finally, using these scattering models, we perform drift-diffusion based transport simulations of a nanowire field-effect transistor and compare the device performances with experimental measurements. Our device modeling provides insight into performance limits of InAs nanowire transistors and can be used as a predictive methodology for nanowire-based integrated circuits.Comment: 22 pages, 5 Figures, Nano Letter

Vertical Integration of Germanium Nanowires on Silicon Substrates for Nanoelectronics.

Rapid development of semiconductor industry in recent years has been primarily driven by continuous scaling. As the size of the transistors approaches tens of nanometers, we are faced with challenges due to technological and economic reasons. To this end, unconventional semiconductor materials and novel device structures have attracted a lot of interests as promising candidates to replace the Si-channel MOSFET and help extend Moore’s law. In this dissertation, we focus on chemically-synthesized germanium nanowires, and investigate their potential as electronic devices, especially when vertically integrated on a Si substrate. The contributions of the work are as follows: First, the Vapor-Liquid-Solid method for growing Ge nanowires on (111) Si substrates is explored. In addition to the growth of vertical, taper-free, intrinsic Ge nanowires, strategies for doping the nanowires, forming a radial heterojunction and controlling growth sites are also discussed. Second, the Ge/Si heterojunction obtained via nanowire growth is examined by transmission electron microscopy. We confirm the epitaxial nature of the heterojunction despite the 4% lattice mismatch and determine the transition width to be 10-15 nm. Vertical heterodiodes with independently-tuned doping profile in both Ge and Si are demonstrated. Different devices are obtained, including: (1) a rectifying diode with >1,000,000 on/off ratio and ideality factor of 1.16; (2) a tunnel diode with room temperature negative differential resistance, peak current density of 4.57 kA/cm2 and reversed-bias tunnel current of 3.2 µA/µm; (3) a non-ohmic contact due to large valence band offset between Ge and Si. All observed behaviors are very well supported by theoretical analysis of the devices. In addition, a vertical junctionless transistor with Ge/Si core/shell nanowire channel and surrounding gate is demonstrated. High performance p-type transistor behavior with on state current density of 750 µA/µm and mobility of 282 cm2/V∙s is achieved. Moreover, an analytical model is developed to quantitatively explain the measured data and excellent agreement is obtained. Finally, progress towards the realization of a nanowire tunnel transistor is reported. A physical model for nanowire tunnel transistors is proposed. Preliminary experimental results verified that the device concept works although further optimization is still required to boost its performance.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/120872/1/linchen_1.pd

Tunnel Junction-Embedded Field-Effect Transistor for Negative Differential Resistance and Its Multi-Valued Logic and Memory Applications

Device PhysicsI propose a novel negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) by combining pn tunnel diode with transistor. The embedded transistors suppress the valley current with transistor off-leakage current level. With various configurations of pn diode and transistor, single or multiple NDR characteristics obtained and each operation principle is explained clearly. Each composed device is analyzed in detail and NDR characteristics are examined device design parameters. In the single NDR case, operation voltage is below 0.5V, which is good at power density. In the multiple NDR case, band-to-band tunneling (BTBT) in tunnel junction provides the first peak, and second peak and valley are generated from the suppression of diode current by off-state transistor. For the digital applications, introduced tri-state voltage transfer circuit makes NDR device take single input operation. Moreover, by using complementary multiple NDR devices, 5-state memory is demonstrated only with four transistors.ope

Design Consideration And Impact Of Gate Length Variation On Junctionless Strained Double Gate MOSFET

Aggressive scaling of Metal-oxide-semiconductor Field Effect Transistors (MOSFET) have been conducted over the past several decades and now is becoming more intricate due to its scaling limit and short channel effects (SCE). To overcome this adversity, a lot of new transistor structures have been proposed, including multi gate structure, high-k/metal gate stack, strained channel, fully-depleted body and junctionless configuration. This paper describes a comprehensive 2-D simulation design of a proposed transistor that employs all the aforementioned structures, named as Junctionless Strained Double Gate MOSFETs (JLSDGM). Variation in critical design parameter such as gate length (Lg) is considered and its impact on the output properties is comprehensively investigated. The results shows that the variation in gate length (Lg) does contributes a significant impact on the drain current (ID), on-current (ION), off-current (IOFF), ION/IOFF ratio, subthreshold swing (SS) and transconductance (gm). The JLSDGM device with the least investigated gate length (4nm) still provides remarkable device properties in which both ION and gm(max) are measured at 1680 µA/µm and 2.79 mS/µm respectively

Electronic Nanodevices

The start of high-volume production of field-effect transistors with a feature size below 100 nm at the end of the 20th century signaled the transition from microelectronics to nanoelectronics. Since then, downscaling in the semiconductor industry has continued until the recent development of sub-10 nm technologies. The new phenomena and issues as well as the technological challenges of the fabrication and manipulation at the nanoscale have spurred an intense theoretical and experimental research activity. New device structures, operating principles, materials, and measurement techniques have emerged, and new approaches to electronic transport and device modeling have become necessary. Examples are the introduction of vertical MOSFETs in addition to the planar ones to enable the multi-gate approach as well as the development of new tunneling, high-electron mobility, and single-electron devices. The search for new materials such as nanowires, nanotubes, and 2D materials for the transistor channel, dielectrics, and interconnects has been part of the process. New electronic devices, often consisting of nanoscale heterojunctions, have been developed for light emission, transmission, and detection in optoelectronic and photonic systems, as well for new chemical, biological, and environmental sensors. This Special Issue focuses on the design, fabrication, modeling, and demonstration of nanodevices for electronic, optoelectronic, and sensing applications

FABRICATION AND CHARACTERIZATION OF ACTIVE NANOSTRUCTURES

Three different nanostructure active devices have been designed, fabricated and characterized. Junctionless transistors based on highly-doped silicon nanowires fabricated using a bottom-up fabrication approach are first discussed. The fabrication avoids the ion implantation step since silicon nanowires are doped in-situ during growth. Germanium junctionless transistors fabricated with a top down approach starting from a germanium on insulator substrate and using a gate stack of high-k dielectrics and GeO2 are also presented. The levels and origin of low-frequency noise in junctionless transistor devices fabricated from silicon nanowires and also from GeOI devices are reported. Low-frequency noise is an indicator of the quality of the material, hence its characterization can reveal the quality and perhaps reliability of fabricated transistors. A novel method based on low-frequency noise measurement to envisage trap density in the semiconductor bandgap near the semiconductor/oxide interface of nanoscale silicon junctionless transistors (JLTs) is presented. Low-frequency noise characterization of JLTs biased in saturation is conducted at different gate biases. The noise spectrum indicates either a Lorentzian or 1/f. A simple analysis of the low-frequency noise data leads to the density of traps and their energy within the semiconductor bandgap. The level of noise in silicon JLT devices is lower than reported values on transistors fabricated using a top-down approach. This noise level can be significantly improved by improving the quality of dielectric and the channel interface