1,521 research outputs found

    Ring oscillator clocks and margins

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    How much margin do we have to add to the delay lines of a bundled-data circuit? This paper is an attempt to give a methodical answer to this question, taking into account all sources of variability and the existing EDA machinery for timing analysis and sign-off. The paper is based on the study of the margins of a ring oscillator that substitutes a PLL as clock generator. A timing model is proposed that shows that a 12% margin for delay lines can be sufficient to cover variability in a 65nm technology. In a typical scenario, performance and energy improvements between 15% and 35% can be obtained by using a ring oscillator instead of a PLL. The paper concludes that a synchronous circuit with a ring oscillator clock shows similar benefits in performance and energy as those of bundled-data asynchronous circuits.Peer ReviewedPostprint (author's final draft

    A Portable Implementation on Industrial Devices of a Predictive Controller Using Graphical Programming

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    This paper presents an approach for developing an Extended Prediction Self-Adaptive Controller employing graphical programming of industrial standard devices, for controlling fast processes. For comparison purposes, the algorithm has been implemented on three different FPGA (Field Programmable Gate Arrays) chips. The paper presents research aspects regarding graphical programming controller design, showing that a single advanced control application can run on different targets without requiring significant program modifications. Based on the time needed for processing the control signal and on the application, one can efficiently and easily select the most appropriate device. To exemplify the procedure, a conclusive case study is presented

    On-chip signaling techniques for high-speed Serdes transceivers

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    The general goal of the VLSI technology is to produce very fast chips with very low power consumption. The technology scaling along with increasing the working frequency had been the perfect solution, which enabled the evolution of electronic devices in the 20th century. However, in deep sub-micron technologies, the on-chip power density limited the continuous increment in frequency, which led to another trend for designing higher performance chips without increasing the working speed. Parallelism was the optimum solution, and the VLSI manufacturers began the era of multi-core chips. These multi-core chips require a full inter-core network for the required communication. These on-chip links were conventionally parallel. However, due to reverse scaling in modern technologies, parallel signaling is becoming a burden due to the very large area of needed interconnects. Also, due to the very high power due to the tremendous number of repeaters, in addition to cross talk issues. As a solution, on-chip serial communication was suggested. It will solve all the previous issues, but it will require very high speed circuits to achieve the same data rates. This thesis presents two full SerDes transceiver designs for on-chip high speed serial communication. Both designs use long lossy on-chip differential interconnects with capacitive termination. The first design uses a 3-level self-timed signaling technique. This signaling technique is totally jitter-insensitive, since both of the data and clock are extracted at the receiver from the same signal. A new encoding and driving technique is designed to enable the transmitter to work at a frequency equal to the data rate, which is half of the frequency of the previous designs, along with achieving the same data rate. Also, this design generates the third voltage level without the need of an external supply. This design is very tolerant to any possible variations, such as PVT variations or the input clock\u27s duty cycle variations. This transceiver is prepared for tape-out in UMC 0.13μm CMOS technology in June 2014. The second design uses a new 3-level signaling technique; the proposed technique uses a frequency of only half the data rate, which totally relaxes the full transceiver design. The new technique is also self-timed enabling the extraction of both the data, and the clock from the same signal. New encoders and decoders are designed, and a new architecture for a 3-level inverter is presented. This transceiver achieves very high data rates. This new design is expected to be taped-out using the GF 65nm CMOS technology in August 2014

    Fast And Accurate Receiver Jitter Tolerance Extrapolation Using The Q-Factor Linear Fitting Method

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    A performance bit rates of more than 6 Gb/s is deemed as a common standard in high-speed interconnect system in conjunction with the recent enhancement of high-speed serial interface (HSSI). In industry, receiver (Rx) jitter tolerance (JTOL) measurement required to characterize the high-speed interconnect. Time required for conventional methods to complete Rx JTOL measurement for low bit error rate (BER) values normally took a week’s time depending on the data rate. In addition, a large number of bits is required to be transmitted hence resulting measurement cost as inefficient. This research project implements a method known as Q-factor linear fitting method to reduce the measurement time of the Rx JTOL at low BER by using high BER data. The result shows that the measurement of Rx JTOL using Q-factor linear fitting method using BER 10-10 data achieved 11x speed-up in comparison to direct measurement of Rx JTOL. The proposed methods of combined different level of BER values and increase more data points of higher BER able to significantly improve the accuracy of the Rx JTOL measurement result. The proposed method is successfully established in the experiment where the results obtained indicated relative error of Rx JTOL using Q-factor linear fitting method of BER 10-10 data are reduced from 9.47% to 3.31% after combining with the BER 10-11 data and relative error for Rx JTOL extrapolation measurement using BER 10-10 data at low temperature (-25˚C) is reduced from 9.47% to 5.43% by increasing the measurement data point from 20 data points to 30 data point
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