Survey on Combinatorial Register Allocation and Instruction Scheduling

Register allocation (mapping variables to processor registers or memory) and instruction scheduling (reordering instructions to increase instruction-level parallelism) are essential tasks for generating efficient assembly code in a compiler. In the last three decades, combinatorial optimization has emerged as an alternative to traditional, heuristic algorithms for these two tasks. Combinatorial optimization approaches can deliver optimal solutions according to a model, can precisely capture trade-offs between conflicting decisions, and are more flexible at the expense of increased compilation time. This paper provides an exhaustive literature review and a classification of combinatorial optimization approaches to register allocation and instruction scheduling, with a focus on the techniques that are most applied in this context: integer programming, constraint programming, partitioned Boolean quadratic programming, and enumeration. Researchers in compilers and combinatorial optimization can benefit from identifying developments, trends, and challenges in the area; compiler practitioners may discern opportunities and grasp the potential benefit of applying combinatorial optimization

A Survey of Techniques for Improving Security of GPUs

Graphics processing unit (GPU), although a powerful performance-booster, also has many security vulnerabilities. Due to these, the GPU can act as a safe-haven for stealthy malware and the weakest `link' in the security `chain'. In this paper, we present a survey of techniques for analyzing and improving GPU security. We classify the works on key attributes to highlight their similarities and differences. More than informing users and researchers about GPU security techniques, this survey aims to increase their awareness about GPU security vulnerabilities and potential countermeasures

A decoupled local memory allocator

Compilers use software-controlled local memories to provide fast, predictable, and power-efficient access to critical data. We show that the local memory allocation for straight-line, or linearized programs is equivalent to a weighted interval-graph coloring problem. This problem is new when allowing a color interval to "wrap around," and we call it the submarine-building problem. This graph-theoretical decision problem differs slightly from the classical ship-building problem, and exhibits very interesting and unusual complexity properties. We demonstrate that the submarine-building problem is NP-complete, while it is solvable in linear time for not-so-proper interval graphs, an extension of the the class of proper interval graphs. We propose a clustering heuristic to approximate any interval graph into a not-so-proper interval graph, decoupling spill code generation from local memory assignment. We apply this heuristic to a large number of randomly generated interval graphs reproducing the statistical features of standard local memory allocation benchmarks, comparing with state-of-the-art heuristics. © 2013 ACM

CCD Modelling and Verification for ESA's Euclid CCD Architecture

This thesis discusses semiconductor modelling carried out to investigate the charge packets which are present in Charge Coupled Devices (CCDs). The details of charge distribution are of interest for scientific CCDs, in particular those which may become damaged due to the effects of harsh radiation environments such as those experienced in space. Therefore this thesis focuses on the CCDs used in the main focal plane instrument (VIS, a visible imager) on the European Space Agency's Euclid space telescope due for launch in 2018. The thesis is spilt into two parts, with the early chapters concentrating on the development of device models and the interpretation of modelling results. The modelling work is verified in latter chapters to ensure that the model predictions concur with lab based measurements on test devices. Model verification makes up a large part of this thesis, ensuring the accuracy of the models. In some cases initial modelling work was shown to predict parameters different to those measured in test devices, however, investigations are made which show manufacturing errors are partly to blame. During this work images were taken using a Focussed Ion Beam Scanning Electron Microscope (FIBSEM), which allows cross-sectional images of the device to be taken, these showed deviations from the designed ploy silicon electrode geometry, resulting in some undersized and some oversized gates, these reduced the accuracy of some models, which were later modified. Through this investigation a method for predicting gate geometry was developed based on the Silvaco device models. Further testing was carried out to verify the charge packet relationship with CTE in test devices. CTE is measured using the Extended Pixel Edge Response (EPER) technique, which allows CTE to be measured over a range of signal sizes. The CTE data can be used to calculate the charge loss per pixel as an average across the device column and these values can be compared against the charge packet volume simulations